Lines Matching refs:nmk_chip
286 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
291 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset);
292 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset);
297 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
298 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
301 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip,
306 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC);
311 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC);
314 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
319 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
322 nmk_chip->pull_up &= ~BIT(offset);
327 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
330 nmk_chip->pull_up |= BIT(offset);
331 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
333 nmk_chip->pull_up &= ~BIT(offset);
334 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
338 static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
341 bool enabled = nmk_chip->lowemi & BIT(offset);
347 nmk_chip->lowemi |= BIT(offset);
349 nmk_chip->lowemi &= ~BIT(offset);
351 writel_relaxed(nmk_chip->lowemi,
352 nmk_chip->addr + NMK_GPIO_LOWEMI);
355 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
358 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
361 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip,
365 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
367 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
370 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip,
373 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS);
374 __nmk_gpio_set_output(nmk_chip, offset, val);
377 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
381 u32 rwimsc = nmk_chip->rwimsc;
382 u32 fwimsc = nmk_chip->fwimsc;
384 if (glitch && nmk_chip->set_ioforce) {
388 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
389 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
391 nmk_chip->set_ioforce(true);
394 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
396 if (glitch && nmk_chip->set_ioforce) {
397 nmk_chip->set_ioforce(false);
399 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
400 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
405 nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset)
407 u32 falling = nmk_chip->fimsc & BIT(offset);
408 u32 rising = nmk_chip->rimsc & BIT(offset);
409 int gpio = nmk_chip->chip.base + offset;
410 int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset);
420 nmk_chip->rimsc &= ~BIT(offset);
421 writel_relaxed(nmk_chip->rimsc,
422 nmk_chip->addr + NMK_GPIO_RIMSC);
426 nmk_chip->fimsc &= ~BIT(offset);
427 writel_relaxed(nmk_chip->fimsc,
428 nmk_chip->addr + NMK_GPIO_FIMSC);
431 dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio);
612 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
614 clk_enable(nmk_chip->clk);
615 writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC);
616 clk_disable(nmk_chip->clk);
624 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip,
636 rimscval = &nmk_chip->rimsc;
637 fimscval = &nmk_chip->fimsc;
641 rimscval = &nmk_chip->rwimsc;
642 fimscval = &nmk_chip->fwimsc;
646 if (nmk_chip->edge_rising & BIT(offset)) {
651 writel(*rimscval, nmk_chip->addr + rimscreg);
653 if (nmk_chip->edge_falling & BIT(offset)) {
658 writel(*fimscval, nmk_chip->addr + fimscreg);
662 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip,
670 if (nmk_chip->sleepmode && on) {
671 __nmk_gpio_set_slpm(nmk_chip, offset,
675 __nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on);
680 struct nmk_gpio_chip *nmk_chip;
683 nmk_chip = irq_data_get_irq_chip_data(d);
684 if (!nmk_chip)
687 clk_enable(nmk_chip->clk);
689 spin_lock(&nmk_chip->lock);
691 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable);
693 if (!(nmk_chip->real_wake & BIT(d->hwirq)))
694 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable);
696 spin_unlock(&nmk_chip->lock);
698 clk_disable(nmk_chip->clk);
715 struct nmk_gpio_chip *nmk_chip;
718 nmk_chip = irq_data_get_irq_chip_data(d);
719 if (!nmk_chip)
722 clk_enable(nmk_chip->clk);
724 spin_lock(&nmk_chip->lock);
727 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on);
730 nmk_chip->real_wake |= BIT(d->hwirq);
732 nmk_chip->real_wake &= ~BIT(d->hwirq);
734 spin_unlock(&nmk_chip->lock);
736 clk_disable(nmk_chip->clk);
745 struct nmk_gpio_chip *nmk_chip;
748 nmk_chip = irq_data_get_irq_chip_data(d);
749 if (!nmk_chip)
756 clk_enable(nmk_chip->clk);
757 spin_lock_irqsave(&nmk_chip->lock, flags);
760 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false);
763 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false);
765 nmk_chip->edge_rising &= ~BIT(d->hwirq);
767 nmk_chip->edge_rising |= BIT(d->hwirq);
769 nmk_chip->edge_falling &= ~BIT(d->hwirq);
771 nmk_chip->edge_falling |= BIT(d->hwirq);
774 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true);
777 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true);
779 spin_unlock_irqrestore(&nmk_chip->lock, flags);
780 clk_disable(nmk_chip->clk);
787 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
789 clk_enable(nmk_chip->clk);
796 struct nmk_gpio_chip *nmk_chip = irq_data_get_irq_chip_data(d);
799 clk_disable(nmk_chip->clk);
806 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
811 clk_enable(nmk_chip->clk);
812 status = readl(nmk_chip->addr + NMK_GPIO_IS);
813 clk_disable(nmk_chip->clk);
829 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
832 clk_enable(nmk_chip->clk);
834 dir = readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset);
836 clk_disable(nmk_chip->clk);
846 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
848 clk_enable(nmk_chip->clk);
850 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
852 clk_disable(nmk_chip->clk);
859 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
862 clk_enable(nmk_chip->clk);
864 value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
866 clk_disable(nmk_chip->clk);
874 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
876 clk_enable(nmk_chip->clk);
878 __nmk_gpio_set_output(nmk_chip, offset, val);
880 clk_disable(nmk_chip->clk);
886 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
888 clk_enable(nmk_chip->clk);
890 __nmk_gpio_make_output(nmk_chip, offset, val);
892 clk_disable(nmk_chip->clk);
898 static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset)
902 clk_enable(nmk_chip->clk);
904 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset);
905 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset);
907 clk_disable(nmk_chip->clk);
919 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip);
935 clk_enable(nmk_chip->clk);
936 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset));
937 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset));
938 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset));
939 mode = nmk_gpio_get_mode(nmk_chip, offset);
975 if (nmk_chip->edge_rising & BIT(offset))
977 else if (nmk_chip->edge_falling & BIT(offset))
988 clk_disable(nmk_chip->clk);
1021 struct nmk_gpio_chip *nmk_chip;
1041 nmk_chip = nmk_gpio_chips[id];
1042 if (nmk_chip) {
1044 return nmk_chip;
1047 nmk_chip = devm_kzalloc(&pdev->dev, sizeof(*nmk_chip), GFP_KERNEL);
1048 if (!nmk_chip) {
1053 nmk_chip->bank = id;
1054 chip = &nmk_chip->chip;
1066 nmk_chip->addr = base;
1074 nmk_chip->clk = clk;
1076 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips));
1077 nmk_gpio_chips[id] = nmk_chip;
1078 return nmk_chip;
1084 struct nmk_gpio_chip *nmk_chip;
1092 nmk_chip = nmk_gpio_populate_chip(np, dev);
1093 if (IS_ERR(nmk_chip)) {
1095 return PTR_ERR(nmk_chip);
1102 dev->id = nmk_chip->bank;
1109 * The virt address in nmk_chip->addr is in the nomadik register space,
1112 nmk_chip->sleepmode = supports_sleepmode;
1113 spin_lock_init(&nmk_chip->lock);
1115 chip = &nmk_chip->chip;
1127 irqchip = &nmk_chip->irqchip;
1154 clk_enable(nmk_chip->clk);
1155 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1156 clk_disable(nmk_chip->clk);
1159 ret = gpiochip_add_data(chip, nmk_chip);
1163 platform_set_drvdata(dev, nmk_chip);
1543 * nmk_chip we're using that as backup)
1575 struct nmk_gpio_chip *nmk_chip;
1578 nmk_chip = find_nmk_gpio_from_pin(g->pins[i]);
1579 if (!nmk_chip) {
1587 clk_enable(nmk_chip->clk);
1596 nmk_gpio_disable_lazy_irq(nmk_chip, bit);
1598 __nmk_gpio_set_mode_safe(nmk_chip, bit,
1600 clk_disable(nmk_chip->clk);
1632 struct nmk_gpio_chip *nmk_chip;
1645 nmk_chip = gpiochip_get_data(chip);
1649 clk_enable(nmk_chip->clk);
1652 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1653 clk_disable(nmk_chip->clk);
1699 struct nmk_gpio_chip *nmk_chip;
1705 nmk_chip = find_nmk_gpio_from_pin(pin);
1706 if (!nmk_chip) {
1746 dev_dbg(nmk_chip->chip.parent,
1755 dev_dbg(nmk_chip->chip.parent,
1762 clk_enable(nmk_chip->clk);
1766 __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1768 __nmk_gpio_make_output(nmk_chip, bit, val);
1770 __nmk_gpio_make_input(nmk_chip, bit);
1771 __nmk_gpio_set_pull(nmk_chip, bit, pull);
1774 __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1776 __nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1777 clk_disable(nmk_chip->clk);
1871 struct nmk_gpio_chip *nmk_chip;
1878 nmk_chip = nmk_gpio_populate_chip(gpio_np, pdev);
1879 if (IS_ERR(nmk_chip))