Lines Matching refs:base
48 * There are two base address for pull related configuration
49 * in mt8135, and different GPIO pins use different base address.
51 * should use the second base address.
782 return pinctrl_gpio_direction_input(chip->base + offset);
789 return pinctrl_gpio_direction_output(chip->base + offset);
996 pctl->eint->base = devm_platform_ioremap_resource(pdev, 0);
997 if (IS_ERR(pctl->eint->base))
998 return PTR_ERR(pctl->eint->base);
1052 /* Only 8135 has two base addr, other SoCs have only one. */
1100 pctl->chip->base = -1;