Lines Matching refs:value
259 u32 value;
261 value = ioread32(ioxapic_use);
264 return !!(value & BIT(offset - 8 + 0));
266 return !!(value & BIT(offset - 13 + 3));
268 return !!(value & BIT(offset - 45 + 5));
307 u32 value, mode;
309 value = ioread32(reg);
311 mode = value & USE_SEL_MASK;
317 seq_printf(s, "0x%08x 0x%08x", value, ioread32(conf2));
371 u32 value;
373 value = ioread32(reg);
375 value &= ~USE_SEL_MASK;
377 value |= grp->modes[i];
379 value |= grp->mode;
381 iowrite32(value, reg);
407 u32 value;
417 value = ioread32(reg);
418 if ((value & USE_SEL_MASK) != USE_SEL_GPIO) {
419 iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg);
456 u32 value;
460 value = ioread32(reg);
461 value &= ~DIR_BIT;
463 value |= DIR_BIT;
474 iowrite32(value, reg);
498 u32 value, pull;
502 value = ioread32(conf2);
505 pull = value & GPIWP_MASK;
541 u32 value;
545 value = ioread32(conf2);
552 value &= ~GPIWP_MASK;
555 value &= ~GPIWP_MASK;
556 value |= GPIWP_DOWN;
559 value &= ~GPIWP_MASK;
560 value |= GPIWP_UP;
571 iowrite32(value, conf2);
597 static void lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
605 if (value)
619 int value)
621 lp_gpio_set(chip, offset, value);
718 u32 value;
730 value = ioread32(reg);
734 value &= ~(TRIG_SEL_BIT | INT_INV_BIT);
738 value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT;
742 value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT;
746 value |= TRIG_SEL_BIT | INT_INV_BIT;
748 iowrite32(value, reg);