Lines Matching refs:value
217 u32 value;
238 value = readl(community->regs + offset);
239 if (value & BIT(gpp_offset))
243 value = readl(community->regs + offset);
244 if (value & BIT(gpp_offset))
394 u32 value;
397 value = readl(padcfg0);
399 value &= ~PADCFG0_PMODE_MASK;
402 value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
404 value |= grp->mode << PADCFG0_PMODE_SHIFT;
406 writel(value, padcfg0);
416 u32 value;
418 value = readl(padcfg0);
420 value &= ~PADCFG0_GPIORXDIS;
421 value |= PADCFG0_GPIOTXDIS;
423 value &= ~PADCFG0_GPIOTXDIS;
424 value |= PADCFG0_GPIORXDIS;
426 writel(value, padcfg0);
429 static int __intel_gpio_get_gpio_mode(u32 value)
431 return (value & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
441 u32 value;
443 value = readl(padcfg0);
446 value &= ~PADCFG0_PMODE_MASK;
447 value |= PADCFG0_PMODE_GPIO;
450 value &= ~PADCFG0_GPIORXDIS;
451 value |= PADCFG0_GPIOTXDIS;
454 value &= ~(PADCFG0_GPIROUTIOXAPIC | PADCFG0_GPIROUTSCI);
455 value &= ~(PADCFG0_GPIROUTSMI | PADCFG0_GPIROUTNMI);
457 writel(value, padcfg0);
532 u32 value, term;
538 value = readl(padcfg1);
541 term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
550 if (!term || !(value & PADCFG1_TERM_UP))
571 if (!term || value & PADCFG1_TERM_UP)
669 u32 value;
676 value = readl(padcfg1);
680 value &= ~(PADCFG1_TERM_MASK | PADCFG1_TERM_UP);
684 value &= ~PADCFG1_TERM_MASK;
686 value |= PADCFG1_TERM_UP;
688 /* Set default strength value in case none is given */
694 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
697 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
700 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
703 value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
712 value &= ~(PADCFG1_TERM_UP | PADCFG1_TERM_MASK);
714 /* Set default strength value in case none is given */
720 value |= PADCFG1_TERM_20K << PADCFG1_TERM_SHIFT;
723 value |= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
730 value |= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
737 value |= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
747 writel(value, padcfg1);
937 int value)
955 if (value)
997 int value)
999 intel_gpio_set(chip, offset, value);
1050 u32 value;
1063 value = readl(reg);
1065 value &= ~BIT(gpp_offset);
1067 value |= BIT(gpp_offset);
1068 writel(value, reg);
1090 u32 value;
1110 value = readl(reg);
1112 value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
1115 value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
1117 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1118 value |= PADCFG0_RXINV;
1120 value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
1123 value |= PADCFG0_RXINV;
1125 value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
1128 writel(value, reg);
1609 static bool __intel_gpio_is_direct_irq(u32 value)
1611 return (value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) &&
1612 (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO);
1618 u32 value;
1639 * after suspend, i.e. by an unknown reason the Rx value becomes
1647 value = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
1648 if (__intel_gpio_is_direct_irq(value))
1699 static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
1705 updated = (curr & ~mask) | (value & mask);
1781 * check the saved value for the Direct IRQ mode.