Lines Matching refs:vg
543 static struct intel_community *byt_get_community(struct intel_pinctrl *vg,
549 for (i = 0; i < vg->ncommunities; i++) {
550 comm = vg->communities + i;
558 static void __iomem *byt_gpio_reg(struct intel_pinctrl *vg, unsigned int offset,
561 struct intel_community *comm = byt_get_community(vg, offset);
585 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
587 return vg->soc->ngroups;
593 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
595 return vg->soc->groups[selector].name;
603 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
605 *pins = vg->soc->groups[selector].pins;
606 *num_pins = vg->soc->groups[selector].npins;
619 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
621 return vg->soc->nfunctions;
627 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
629 return vg->soc->functions[selector].name;
637 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
639 *groups = vg->soc->functions[selector].groups;
640 *num_groups = vg->soc->functions[selector].ngroups;
645 static void byt_set_group_simple_mux(struct intel_pinctrl *vg,
658 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
660 dev_warn(vg->dev,
675 static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,
688 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
690 dev_warn(vg->dev,
708 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctldev);
709 const struct intel_function func = vg->soc->functions[func_selector];
710 const struct intel_pingroup group = vg->soc->groups[group_selector];
713 byt_set_group_mixed_mux(vg, group, group.modes);
715 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
717 byt_set_group_simple_mux(vg, group, group.mode);
722 static u32 byt_get_gpio_mux(struct intel_pinctrl *vg, unsigned int offset)
725 if (!strcmp(vg->soc->uid, BYT_SCORE_ACPI_UID) &&
730 if (!strcmp(vg->soc->uid, BYT_SUS_ACPI_UID) &&
737 static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int offset)
739 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
760 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
761 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
777 gpio_mux = byt_get_gpio_mux(vg, offset);
783 dev_warn(vg->dev, FW_BUG "pin %u forcibly re-configured as GPIO\n", offset);
788 pm_runtime_get(vg->dev);
797 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
799 byt_gpio_clear_triggering(vg, offset);
800 pm_runtime_put(vg->dev);
803 static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg,
806 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
815 dev_info_once(vg->dev, "Potential Error: Setting GPIO with direct_irq_en to output");
823 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
824 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
835 byt_gpio_direct_irq_check(vg, offset);
899 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
901 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
902 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
903 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
984 struct intel_pinctrl *vg = pinctrl_dev_get_drvdata(pctl_dev);
986 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
987 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
988 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
1018 dev_warn(vg->dev,
1040 dev_warn(vg->dev,
1127 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1128 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1141 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1142 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1160 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1161 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1182 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1183 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1207 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1208 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1214 byt_gpio_direct_irq_check(vg, offset);
1231 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1235 for (i = 0; i < vg->soc->npins; i++) {
1245 pin = vg->soc->pins[i].number;
1246 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1256 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1266 comm = byt_get_community(vg, pin);
1341 struct intel_pinctrl *vg = gpiochip_get_data(gc);
1345 reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
1357 struct intel_pinctrl *vg = gpiochip_get_data(gc);
1359 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
1365 struct intel_pinctrl *vg = gpiochip_get_data(gc);
1371 reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1403 struct intel_pinctrl *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1407 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1409 if (!reg || offset >= vg->chip.ngpio)
1442 struct intel_pinctrl *vg = gpiochip_get_data(irq_desc_get_handler_data(desc));
1450 for (base = 0; base < vg->chip.ngpio; base += 32) {
1451 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1454 dev_warn(vg->dev,
1464 virq = irq_find_mapping(vg->chip.irq.domain, base + pin);
1475 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1485 for (i = 0; i < vg->soc->npins; i++) {
1486 unsigned int pin = vg->soc->pins[i].number;
1488 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1490 dev_warn(vg->dev,
1499 dev_dbg(vg->dev, "excluding GPIO %d from IRQ domain\n", i);
1500 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1501 byt_gpio_clear_triggering(vg, i);
1502 dev_dbg(vg->dev, "disabling GPIO %d\n", i);
1509 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1514 for (base = 0; base < vg->soc->npins; base += 32) {
1515 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1518 dev_warn(vg->dev,
1529 dev_err(vg->dev,
1539 struct intel_pinctrl *vg = gpiochip_get_data(chip);
1540 struct device *dev = vg->dev;
1543 ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, vg->soc->npins);
1550 static int byt_gpio_probe(struct intel_pinctrl *vg)
1552 struct platform_device *pdev = to_platform_device(vg->dev);
1557 vg->chip = byt_gpio_chip;
1558 gc = &vg->chip;
1559 gc->label = dev_name(vg->dev);
1563 gc->parent = vg->dev;
1564 gc->ngpio = vg->soc->npins;
1567 vg->context.pads = devm_kcalloc(vg->dev, gc->ngpio, sizeof(*vg->context.pads),
1569 if (!vg->context.pads)
1578 vg->irqchip.name = "BYT-GPIO",
1579 vg->irqchip.irq_ack = byt_irq_ack,
1580 vg->irqchip.irq_mask = byt_irq_mask,
1581 vg->irqchip.irq_unmask = byt_irq_unmask,
1582 vg->irqchip.irq_set_type = byt_irq_type,
1583 vg->irqchip.flags = IRQCHIP_SKIP_SET_WAKE,
1586 girq->chip = &vg->irqchip;
1591 girq->parents = devm_kcalloc(vg->dev, girq->num_parents,
1600 ret = devm_gpiochip_add_data(vg->dev, gc, vg);
1602 dev_err(vg->dev, "failed adding byt-gpio chip\n");
1609 static int byt_set_soc_data(struct intel_pinctrl *vg,
1612 struct platform_device *pdev = to_platform_device(vg->dev);
1615 vg->soc = soc;
1617 vg->ncommunities = vg->soc->ncommunities;
1618 vg->communities = devm_kcalloc(vg->dev, vg->ncommunities,
1619 sizeof(*vg->communities), GFP_KERNEL);
1620 if (!vg->communities)
1623 for (i = 0; i < vg->soc->ncommunities; i++) {
1624 struct intel_community *comm = vg->communities + i;
1626 *comm = vg->soc->communities[i];
1646 struct intel_pinctrl *vg;
1653 vg = devm_kzalloc(dev, sizeof(*vg), GFP_KERNEL);
1654 if (!vg)
1657 vg->dev = dev;
1658 ret = byt_set_soc_data(vg, soc_data);
1664 vg->pctldesc = byt_pinctrl_desc;
1665 vg->pctldesc.name = dev_name(dev);
1666 vg->pctldesc.pins = vg->soc->pins;
1667 vg->pctldesc.npins = vg->soc->npins;
1669 vg->pctldev = devm_pinctrl_register(dev, &vg->pctldesc, vg);
1670 if (IS_ERR(vg->pctldev)) {
1672 return PTR_ERR(vg->pctldev);
1675 ret = byt_gpio_probe(vg);
1679 platform_set_drvdata(pdev, vg);
1688 struct intel_pinctrl *vg = dev_get_drvdata(dev);
1694 for (i = 0; i < vg->soc->npins; i++) {
1697 unsigned int pin = vg->soc->pins[i].number;
1699 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1701 dev_warn(vg->dev,
1707 vg->context.pads[i].conf0 = value;
1709 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1711 vg->context.pads[i].val = value;
1720 struct intel_pinctrl *vg = dev_get_drvdata(dev);
1726 for (i = 0; i < vg->soc->npins; i++) {
1729 unsigned int pin = vg->soc->pins[i].number;
1731 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1733 dev_warn(vg->dev,
1740 vg->context.pads[i].conf0) {
1742 value |= vg->context.pads[i].conf0;
1747 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1750 vg->context.pads[i].val) {
1754 v |= vg->context.pads[i].val;