Lines Matching refs:pinctrl
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinconf-generic.h>
22 #include <linux/pinctrl/pinctrl.h>
23 #include <linux/pinctrl/pinmux.h>
28 #include "../pinctrl-utils.h"
106 * Northstar2 IOMUX pinctrl core
503 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
505 return pinctrl->num_groups;
511 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
513 return pinctrl->groups[selector].name;
520 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
522 *pins = pinctrl->groups[selector].pins;
523 *num_pins = pinctrl->groups[selector].num_pins;
545 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
547 return pinctrl->num_functions;
553 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
555 return pinctrl->functions[selector].name;
563 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
565 *groups = pinctrl->functions[selector].groups;
566 *num_groups = pinctrl->functions[selector].num_groups;
571 static int ns2_pinmux_set(struct ns2_pinctrl *pinctrl,
597 dev_err(pinctrl->dev,
599 dev_err(pinctrl->dev, "func:%s grp:%s\n",
615 base_address = pinctrl->base0;
619 base_address = pinctrl->base1;
626 spin_lock_irqsave(&pinctrl->lock, flags);
631 spin_unlock_irqrestore(&pinctrl->lock, flags);
639 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
643 if (grp_select >= pinctrl->num_groups ||
644 func_select >= pinctrl->num_functions)
647 func = &pinctrl->functions[func_select];
648 grp = &pinctrl->groups[grp_select];
656 return ns2_pinmux_set(pinctrl, func, grp, pinctrl->mux_log);
662 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
668 base_address = pinctrl->pinconf_base;
669 spin_lock_irqsave(&pinctrl->lock, flags);
677 spin_unlock_irqrestore(&pinctrl->lock, flags);
685 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
690 spin_lock_irqsave(&pinctrl->lock, flags);
691 enable = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
694 spin_unlock_irqrestore(&pinctrl->lock, flags);
708 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
714 base_address = pinctrl->pinconf_base;
715 spin_lock_irqsave(&pinctrl->lock, flags);
723 spin_unlock_irqrestore(&pinctrl->lock, flags);
732 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
737 spin_lock_irqsave(&pinctrl->lock, flags);
738 val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
740 spin_unlock_irqrestore(&pinctrl->lock, flags);
749 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
755 base_address = pinctrl->pinconf_base;
756 spin_lock_irqsave(&pinctrl->lock, flags);
765 spin_unlock_irqrestore(&pinctrl->lock, flags);
776 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
781 spin_lock_irqsave(&pinctrl->lock, flags);
782 val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
792 spin_unlock_irqrestore(&pinctrl->lock, flags);
798 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
808 base_address = pinctrl->pinconf_base;
809 spin_lock_irqsave(&pinctrl->lock, flags);
814 spin_unlock_irqrestore(&pinctrl->lock, flags);
824 struct ns2_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrldev);
829 spin_lock_irqsave(&pinctrl->lock, flags);
830 val = readl(pinctrl->pinconf_base + pin_data->pin_conf.offset);
834 spin_unlock_irqrestore(&pinctrl->lock, flags);
982 static int ns2_mux_log_init(struct ns2_pinctrl *pinctrl)
987 pinctrl->mux_log = devm_kcalloc(pinctrl->dev, NS2_NUM_IOMUX,
990 if (!pinctrl->mux_log)
994 pinctrl->mux_log[i].is_configured = false;
996 log = &pinctrl->mux_log[0];
1008 log = &pinctrl->mux_log[i];
1020 log = &pinctrl->mux_log[(NS2_NUM_IOMUX - NS2_NUM_PWM_MUX) + i];
1031 struct ns2_pinctrl *pinctrl;
1037 pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
1038 if (!pinctrl)
1041 pinctrl->dev = &pdev->dev;
1042 platform_set_drvdata(pdev, pinctrl);
1043 spin_lock_init(&pinctrl->lock);
1045 pinctrl->base0 = devm_platform_ioremap_resource(pdev, 0);
1046 if (IS_ERR(pinctrl->base0))
1047 return PTR_ERR(pinctrl->base0);
1052 pinctrl->base1 = devm_ioremap(&pdev->dev, res->start,
1054 if (!pinctrl->base1) {
1059 pinctrl->pinconf_base = devm_platform_ioremap_resource(pdev, 2);
1060 if (IS_ERR(pinctrl->pinconf_base))
1061 return PTR_ERR(pinctrl->pinconf_base);
1063 ret = ns2_mux_log_init(pinctrl);
1079 pinctrl->groups = ns2_pin_groups;
1080 pinctrl->num_groups = ARRAY_SIZE(ns2_pin_groups);
1081 pinctrl->functions = ns2_pin_functions;
1082 pinctrl->num_functions = ARRAY_SIZE(ns2_pin_functions);
1086 pinctrl->pctl = pinctrl_register(&ns2_pinctrl_desc, &pdev->dev,
1087 pinctrl);
1088 if (IS_ERR(pinctrl->pctl)) {
1089 dev_err(&pdev->dev, "unable to register IOMUX pinctrl\n");
1090 return PTR_ERR(pinctrl->pctl);