Lines Matching defs:pctrl
69 static u32 owl_read_field(struct owl_pinctrl *pctrl, u32 reg,
74 tmp = readl_relaxed(pctrl->base + reg);
80 static void owl_write_field(struct owl_pinctrl *pctrl, u32 reg, u32 arg,
88 owl_update_bits(pctrl->base + reg, mask, (arg << bit));
93 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
95 return pctrl->soc->ngroups;
101 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
103 return pctrl->soc->groups[group].name;
111 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
113 *pins = pctrl->soc->groups[group].pads;
114 *num_pins = pctrl->soc->groups[group].npads;
123 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
125 seq_printf(s, "%s", dev_name(pctrl->dev));
139 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
141 return pctrl->soc->nfunctions;
147 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
149 return pctrl->soc->functions[function].name;
157 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
159 *groups = pctrl->soc->functions[function].groups;
160 *num_groups = pctrl->soc->functions[function].ngroups;
196 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
201 g = &pctrl->soc->groups[group];
206 raw_spin_lock_irqsave(&pctrl->lock, flags);
208 owl_update_bits(pctrl->base + g->mfpctl_reg, mask, val);
210 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
258 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
263 info = &pctrl->soc->padinfo[pin];
269 arg = owl_read_field(pctrl, reg, bit, width);
271 if (!pctrl->soc->padctl_val2arg)
274 ret = pctrl->soc->padctl_val2arg(info, param, &arg);
288 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
295 info = &pctrl->soc->padinfo[pin];
305 if (!pctrl->soc->padctl_arg2val)
308 ret = pctrl->soc->padctl_arg2val(info, param, &arg);
312 raw_spin_lock_irqsave(&pctrl->lock, flags);
314 owl_write_field(pctrl, reg, arg, bit, width);
316 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
427 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
432 g = &pctrl->soc->groups[group];
438 arg = owl_read_field(pctrl, reg, bit, width);
455 struct owl_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctrldev);
461 g = &pctrl->soc->groups[group];
476 raw_spin_lock_irqsave(&pctrl->lock, flags);
478 owl_write_field(pctrl, reg, arg, bit, width);
480 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
502 owl_gpio_get_port(struct owl_pinctrl *pctrl, unsigned int *pin)
506 for (i = 0; i < pctrl->soc->nports; i++) {
507 const struct owl_gpio_port *port = &pctrl->soc->ports[i];
536 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
541 port = owl_gpio_get_port(pctrl, &offset);
545 gpio_base = pctrl->base + port->offset;
551 raw_spin_lock_irqsave(&pctrl->lock, flags);
553 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
560 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
565 port = owl_gpio_get_port(pctrl, &offset);
569 gpio_base = pctrl->base + port->offset;
571 raw_spin_lock_irqsave(&pctrl->lock, flags);
577 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
582 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
588 port = owl_gpio_get_port(pctrl, &offset);
592 gpio_base = pctrl->base + port->offset;
594 raw_spin_lock_irqsave(&pctrl->lock, flags);
596 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
603 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
608 port = owl_gpio_get_port(pctrl, &offset);
612 gpio_base = pctrl->base + port->offset;
614 raw_spin_lock_irqsave(&pctrl->lock, flags);
616 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
621 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
626 port = owl_gpio_get_port(pctrl, &offset);
630 gpio_base = pctrl->base + port->offset;
632 raw_spin_lock_irqsave(&pctrl->lock, flags);
635 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
643 struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
648 port = owl_gpio_get_port(pctrl, &offset);
652 gpio_base = pctrl->base + port->offset;
654 raw_spin_lock_irqsave(&pctrl->lock, flags);
658 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
663 static void irq_set_type(struct owl_pinctrl *pctrl, int gpio, unsigned int type)
678 if (owl_gpio_get(&pctrl->chip, gpio))
704 port = owl_gpio_get_port(pctrl, &gpio);
708 gpio_base = pctrl->base + port->offset;
710 raw_spin_lock_irqsave(&pctrl->lock, flags);
718 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
724 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
731 port = owl_gpio_get_port(pctrl, &gpio);
735 gpio_base = pctrl->base + port->offset;
737 raw_spin_lock_irqsave(&pctrl->lock, flags);
747 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
753 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
760 port = owl_gpio_get_port(pctrl, &gpio);
764 gpio_base = pctrl->base + port->offset;
765 raw_spin_lock_irqsave(&pctrl->lock, flags);
776 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
782 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
794 irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_FALLING);
796 irq_set_type(pctrl, gpio, IRQ_TYPE_EDGE_RISING);
799 port = owl_gpio_get_port(pctrl, &gpio);
803 gpio_base = pctrl->base + port->offset;
805 raw_spin_lock_irqsave(&pctrl->lock, flags);
810 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
816 struct owl_pinctrl *pctrl = gpiochip_get_data(gc);
823 irq_set_type(pctrl, data->hwirq, type);
830 struct owl_pinctrl *pctrl = irq_desc_get_handler_data(desc);
832 struct irq_domain *domain = pctrl->chip.irq.domain;
841 for (i = 0; i < pctrl->soc->nports; i++) {
842 port = &pctrl->soc->ports[i];
843 base = pctrl->base + port->offset;
846 if (parent != pctrl->irq[i])
866 static int owl_gpio_init(struct owl_pinctrl *pctrl)
872 chip = &pctrl->chip;
874 chip->ngpio = pctrl->soc->ngpios;
875 chip->label = dev_name(pctrl->dev);
876 chip->parent = pctrl->dev;
878 chip->of_node = pctrl->dev->of_node;
880 pctrl->irq_chip.name = chip->of_node->name;
881 pctrl->irq_chip.irq_ack = owl_gpio_irq_ack;
882 pctrl->irq_chip.irq_mask = owl_gpio_irq_mask;
883 pctrl->irq_chip.irq_unmask = owl_gpio_irq_unmask;
884 pctrl->irq_chip.irq_set_type = owl_gpio_irq_set_type;
887 gpio_irq->chip = &pctrl->irq_chip;
891 gpio_irq->parent_handler_data = pctrl;
892 gpio_irq->num_parents = pctrl->num_irq;
893 gpio_irq->parents = pctrl->irq;
895 gpio_irq->map = devm_kcalloc(pctrl->dev, chip->ngpio,
900 for (i = 0, offset = 0; i < pctrl->soc->nports; i++) {
901 const struct owl_gpio_port *port = &pctrl->soc->ports[i];
909 ret = gpiochip_add_data(&pctrl->chip, pctrl);
911 dev_err(pctrl->dev, "failed to register gpiochip\n");
921 struct owl_pinctrl *pctrl;
924 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
925 if (!pctrl)
928 pctrl->base = devm_platform_ioremap_resource(pdev, 0);
929 if (IS_ERR(pctrl->base))
930 return PTR_ERR(pctrl->base);
933 pctrl->clk = devm_clk_get(&pdev->dev, NULL);
934 if (IS_ERR(pctrl->clk)) {
936 return PTR_ERR(pctrl->clk);
939 ret = clk_prepare_enable(pctrl->clk);
945 raw_spin_lock_init(&pctrl->lock);
951 pctrl->chip.direction_input = owl_gpio_direction_input;
952 pctrl->chip.direction_output = owl_gpio_direction_output;
953 pctrl->chip.get = owl_gpio_get;
954 pctrl->chip.set = owl_gpio_set;
955 pctrl->chip.request = owl_gpio_request;
956 pctrl->chip.free = owl_gpio_free;
958 pctrl->soc = soc_data;
959 pctrl->dev = &pdev->dev;
961 pctrl->pctrldev = devm_pinctrl_register(&pdev->dev,
962 &owl_pinctrl_desc, pctrl);
963 if (IS_ERR(pctrl->pctrldev)) {
965 ret = PTR_ERR(pctrl->pctrldev);
973 pctrl->num_irq = ret;
975 pctrl->irq = devm_kcalloc(&pdev->dev, pctrl->num_irq,
976 sizeof(*pctrl->irq), GFP_KERNEL);
977 if (!pctrl->irq) {
982 for (i = 0; i < pctrl->num_irq ; i++) {
986 pctrl->irq[i] = ret;
989 ret = owl_gpio_init(pctrl);
993 platform_set_drvdata(pdev, pctrl);
998 clk_disable_unprepare(pctrl->clk);