Lines Matching defs:lane
152 #define XPSGTR_TYPE_SATA_0 2 /* SATA controller lane 0 */
153 #define XPSGTR_TYPE_SATA_1 3 /* SATA controller lane 1 */
154 #define XPSGTR_TYPE_PCIE_0 4 /* PCIe controller lane 0 */
155 #define XPSGTR_TYPE_PCIE_1 5 /* PCIe controller lane 1 */
156 #define XPSGTR_TYPE_PCIE_2 6 /* PCIe controller lane 2 */
157 #define XPSGTR_TYPE_PCIE_3 7 /* PCIe controller lane 3 */
158 #define XPSGTR_TYPE_DP_0 8 /* Display Port controller lane 0 */
159 #define XPSGTR_TYPE_DP_1 9 /* Display Port controller lane 1 */
171 * struct xpsgtr_ssc - structure to hold SSC settings for a lane
185 * struct xpsgtr_phy - representation of a lane
187 * @type: controller which uses this lane
188 * @lane: lane number
189 * @protocol: protocol in which the lane operates
197 u8 lane;
276 + gtr_phy->lane * PHY_REG_OFFSET + reg;
285 + gtr_phy->lane * PHY_REG_OFFSET + reg;
294 + gtr_phy->lane * PHY_REG_OFFSET + reg;
331 "lane %u (type %u, protocol %u): PLL lock timeout\n",
332 gtr_phy->lane, gtr_phy->type, gtr_phy->protocol);
346 xpsgtr_clr_set(gtr_phy->dev, PLL_REF_SEL(gtr_phy->lane),
349 /* Enable lane clock sharing, if required */
350 if (gtr_phy->refclk != gtr_phy->lane) {
352 xpsgtr_clr_set(gtr_phy->dev, L0_Ln_REF_CLK_SEL(gtr_phy->lane),
386 /* Configure the lane protocol. */
392 switch (gtr_phy->lane) {
408 /* We already checked 0 <= lane <= 3 */
440 writel(gtr_phy->lane, gtr_dev->siou + SATA_CONTROL_OFFSET);
447 u32 mask = PROT_BUS_WIDTH_MASK(gtr_phy->lane);
448 u32 val = PROT_BUS_WIDTH_10 << PROT_BUS_WIDTH_SHIFT(gtr_phy->lane);
489 * shutdown during suspend or when gt lane is changed from current one)
519 * we need to configure any lane ICM_CFG to valid protocol. This
589 * Configure the PLL, the lane protocol, and perform protocol-specific
631 * lane 0 last.
664 /* Set the lane type and protocol based on the PHY type and instance number. */
775 * Get the PHY parameters from the OF arguments and derive the lane
780 dev_err(dev, "Invalid lane number %u\n", phy_lane);
804 * Ensure that the Interconnect Matrix is obeyed, i.e a given lane type
805 * is allowed to operate on the lane.
952 gtr_phy->lane = port;