Lines Matching defs:control_phy
27 struct omap_control_phy *control_phy;
34 control_phy = dev_get_drvdata(dev);
35 if (!control_phy) {
40 if (control_phy->type != OMAP_CTRL_TYPE_PCIE) {
45 val = readl(control_phy->pcie_pcs);
49 writel(val, control_phy->pcie_pcs);
62 struct omap_control_phy *control_phy;
69 control_phy = dev_get_drvdata(dev);
70 if (!control_phy) {
75 if (control_phy->type == OMAP_CTRL_TYPE_OTGHS)
78 val = readl(control_phy->power);
80 switch (control_phy->type) {
90 rate = clk_get_rate(control_phy->sys_clk);
129 __func__, control_phy->type);
133 writel(val, control_phy->power);
273 struct omap_control_phy *control_phy;
279 control_phy = devm_kzalloc(&pdev->dev, sizeof(*control_phy),
281 if (!control_phy)
284 control_phy->dev = &pdev->dev;
285 control_phy->type = *(enum omap_control_phy_type *)of_id->data;
287 if (control_phy->type == OMAP_CTRL_TYPE_OTGHS) {
290 control_phy->otghs_control = devm_ioremap_resource(
292 if (IS_ERR(control_phy->otghs_control))
293 return PTR_ERR(control_phy->otghs_control);
297 control_phy->power = devm_ioremap_resource(&pdev->dev, res);
298 if (IS_ERR(control_phy->power)) {
300 return PTR_ERR(control_phy->power);
304 if (control_phy->type == OMAP_CTRL_TYPE_PIPE3 ||
305 control_phy->type == OMAP_CTRL_TYPE_PCIE) {
306 control_phy->sys_clk = devm_clk_get(control_phy->dev,
308 if (IS_ERR(control_phy->sys_clk)) {
314 if (control_phy->type == OMAP_CTRL_TYPE_PCIE) {
317 control_phy->pcie_pcs = devm_ioremap_resource(&pdev->dev, res);
318 if (IS_ERR(control_phy->pcie_pcs))
319 return PTR_ERR(control_phy->pcie_pcs);
322 dev_set_drvdata(control_phy->dev, control_phy);