Lines Matching defs:wiz
202 struct wiz {
229 static int wiz_reset(struct wiz *wiz)
233 ret = regmap_field_write(wiz->por_en, 0x1);
239 ret = regmap_field_write(wiz->por_en, 0x0);
246 static int wiz_mode_select(struct wiz *wiz)
248 u32 num_lanes = wiz->num_lanes;
254 if (wiz->lane_phy_type[i] == PHY_TYPE_DP)
259 ret = regmap_field_write(wiz->p_standard_mode[i], mode);
267 static int wiz_init_raw_interface(struct wiz *wiz, bool enable)
269 u32 num_lanes = wiz->num_lanes;
274 ret = regmap_field_write(wiz->p_align[i], enable);
278 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);
286 static int wiz_init(struct wiz *wiz)
288 struct device *dev = wiz->dev;
291 ret = wiz_reset(wiz);
297 ret = wiz_mode_select(wiz);
303 ret = wiz_init_raw_interface(wiz, true);
312 static int wiz_regfield_init(struct wiz *wiz)
316 struct regmap *regmap = wiz->regmap;
317 int num_lanes = wiz->num_lanes;
318 struct device *dev = wiz->dev;
321 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
322 if (IS_ERR(wiz->por_en)) {
324 return PTR_ERR(wiz->por_en);
327 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap,
329 if (IS_ERR(wiz->phy_reset_n)) {
331 return PTR_ERR(wiz->phy_reset_n);
334 wiz->pma_cmn_refclk_int_mode =
336 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) {
338 return PTR_ERR(wiz->pma_cmn_refclk_int_mode);
341 wiz->pma_cmn_refclk_mode =
343 if (IS_ERR(wiz->pma_cmn_refclk_mode)) {
345 return PTR_ERR(wiz->pma_cmn_refclk_mode);
348 clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK_DIG_DIV];
356 if (wiz->type == J721E_WIZ_16G) {
357 clk_div_sel = &wiz->clk_div_sel[CMN_REFCLK1_DIG_DIV];
367 clk_mux_sel = &wiz->clk_mux_sel[PLL0_REFCLK];
375 clk_mux_sel = &wiz->clk_mux_sel[PLL1_REFCLK];
383 clk_mux_sel = &wiz->clk_mux_sel[REFCLK_DIG];
384 if (wiz->type == J721E_WIZ_10G)
399 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,
401 if (IS_ERR(wiz->p_enable[i])) {
403 return PTR_ERR(wiz->p_enable[i]);
406 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap,
408 if (IS_ERR(wiz->p_align[i])) {
410 return PTR_ERR(wiz->p_align[i]);
413 wiz->p_raw_auto_start[i] =
415 if (IS_ERR(wiz->p_raw_auto_start[i])) {
418 return PTR_ERR(wiz->p_raw_auto_start[i]);
421 wiz->p_standard_mode[i] =
423 if (IS_ERR(wiz->p_standard_mode[i])) {
426 return PTR_ERR(wiz->p_standard_mode[i]);
430 wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,
432 if (IS_ERR(wiz->typec_ln10_swap)) {
434 return PTR_ERR(wiz->typec_ln10_swap);
465 static int wiz_mux_clk_register(struct wiz *wiz, struct device_node *node,
468 struct device *dev = wiz->dev;
560 static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node,
564 struct device *dev = wiz->dev;
608 static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)
610 struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
620 for (i = 0; i < wiz->clk_div_sel_num; i++) {
627 static int wiz_clock_init(struct wiz *wiz, struct device_node *node)
629 struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
630 struct device *dev = wiz->dev;
647 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);
649 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
660 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);
662 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);
673 ret = wiz_mux_clk_register(wiz, clk_node, clk_mux_sel[i].field,
685 for (i = 0; i < wiz->clk_div_sel_num; i++) {
694 ret = wiz_div_clk_register(wiz, clk_node, clk_div_sel[i].field,
708 wiz_clock_cleanup(wiz, node);
717 struct wiz *wiz = dev_get_drvdata(dev);
721 ret = regmap_field_write(wiz->phy_reset_n, false);
725 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);
733 struct wiz *wiz = dev_get_drvdata(dev);
737 if (id == 0 && wiz->gpio_typec_dir) {
738 if (wiz->typec_dir_delay)
739 msleep_interruptible(wiz->typec_dir_delay);
741 if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
742 regmap_field_write(wiz->typec_ln10_swap, 1);
744 regmap_field_write(wiz->typec_ln10_swap, 0);
748 ret = regmap_field_write(wiz->phy_reset_n, true);
752 if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
753 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
755 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);
774 .compatible = "ti,j721e-wiz-16g", .data = (void *)J721E_WIZ_16G
777 .compatible = "ti,j721e-wiz-10g", .data = (void *)J721E_WIZ_10G
783 static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz)
811 wiz->lane_phy_type[i] = phy_type;
827 struct wiz *wiz;
831 wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL);
832 if (!wiz)
835 wiz->type = (enum wiz_type)of_device_get_match_data(dev);
874 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",
876 if (IS_ERR(wiz->gpio_typec_dir)) {
877 ret = PTR_ERR(wiz->gpio_typec_dir);
884 if (wiz->gpio_typec_dir) {
886 &wiz->typec_dir_delay);
894 wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN;
896 if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN ||
897 wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) {
904 ret = wiz_get_lane_phy_types(dev, wiz);
908 wiz->dev = dev;
909 wiz->regmap = regmap;
910 wiz->num_lanes = num_lanes;
911 if (wiz->type == J721E_WIZ_10G)
912 wiz->clk_mux_sel = clk_mux_sel_10g;
914 wiz->clk_mux_sel = clk_mux_sel_16g;
916 wiz->clk_div_sel = clk_div_sel;
918 if (wiz->type == J721E_WIZ_10G)
919 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G;
921 wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G;
923 platform_set_drvdata(pdev, wiz);
925 ret = wiz_regfield_init(wiz);
931 phy_reset_dev = &wiz->wiz_phy_reset_dev;
952 ret = wiz_clock_init(wiz, node);
958 ret = wiz_init(wiz);
970 wiz->serdes_pdev = serdes_pdev;
976 wiz_clock_cleanup(wiz, node);
993 struct wiz *wiz;
995 wiz = dev_get_drvdata(dev);
996 serdes_pdev = wiz->serdes_pdev;
999 wiz_clock_cleanup(wiz, node);
1010 .name = "wiz",