Lines Matching defs:field
109 struct regmap_field *field;
118 struct regmap_field *field;
126 struct regmap_field *field;
132 struct regmap_field *field;
323 dev_err(dev, "POR_EN reg field init failed\n");
330 dev_err(dev, "PHY_RESET_N reg field init failed\n");
337 dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n");
344 dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n");
349 clk_div_sel->field = devm_regmap_field_alloc(dev, regmap,
351 if (IS_ERR(clk_div_sel->field)) {
352 dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n");
353 return PTR_ERR(clk_div_sel->field);
358 clk_div_sel->field =
361 if (IS_ERR(clk_div_sel->field)) {
362 dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
363 return PTR_ERR(clk_div_sel->field);
368 clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap,
370 if (IS_ERR(clk_mux_sel->field)) {
371 dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n");
372 return PTR_ERR(clk_mux_sel->field);
376 clk_mux_sel->field = devm_regmap_field_alloc(dev, regmap,
378 if (IS_ERR(clk_mux_sel->field)) {
379 dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n");
380 return PTR_ERR(clk_mux_sel->field);
385 clk_mux_sel->field =
389 clk_mux_sel->field =
393 if (IS_ERR(clk_mux_sel->field)) {
394 dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n");
395 return PTR_ERR(clk_mux_sel->field);
402 dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
409 dev_err(dev, "P%d_ALIGN reg field init failed\n", i);
416 dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n",
424 dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n",
433 dev_err(dev, "LN10_SWAP reg field init failed\n");
443 struct regmap_field *field = mux->field;
446 regmap_field_read(field, &val);
453 struct regmap_field *field = mux->field;
457 return regmap_field_write(field, val);
466 struct regmap_field *field, u32 *table)
505 mux->field = field;
524 struct regmap_field *field = div->field;
527 regmap_field_read(field, &val);
544 struct regmap_field *field = div->field;
551 return regmap_field_write(field, val);
561 struct regmap_field *field,
593 div->field = field;
673 ret = wiz_mux_clk_register(wiz, clk_node, clk_mux_sel[i].field,
694 ret = wiz_div_clk_register(wiz, clk_node, clk_div_sel[i].field,