Lines Matching refs:fields
235 struct regmap_field *fields[MAX_FIELDS];
251 ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_ENABLE_STATE);
255 return regmap_field_read_poll_timeout(phy->fields[PLL_OK], val, val,
264 ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_DISABLE_STATE);
274 ret |= regmap_field_write(phy->fields[TX0_ENABLE], TX0_ENABLE_STATE);
277 ret |= regmap_field_write(phy->fields[RX0_ENABLE], RX0_ENABLE_STATE);
290 ret |= regmap_field_write(phy->fields[TX0_ENABLE], TX0_DISABLE_STATE);
293 ret |= regmap_field_write(phy->fields[RX0_ENABLE], RX0_DISABLE_STATE);
320 return regmap_field_read_poll_timeout(phy->fields[CMU_OK_I_0], val,
421 ret |= regmap_field_write(phy->fields[CMU_PLL_CTRL], 0x2);
422 ret |= regmap_field_write(phy->fields[AHB_PMA_CM_VCO_VBIAS_VREG], 0x98);
423 ret |= regmap_field_write(phy->fields[AHB_PMA_CM_VCO_BIAS_VREG], 0x98);
424 ret |= regmap_field_write(phy->fields[AHB_PMA_CM_SR], 0x45);
425 ret |= regmap_field_write(phy->fields[AHB_SSC_GEN_Z_O_20_13], 0xe);
426 ret |= regmap_field_write(phy->fields[LANE_PLL_CTRL_RXEQ_RXIDLE], 0x5);
427 ret |= regmap_field_write(phy->fields[AHB_PMA_LN_AGC_THSEL_VREGH], 0x83);
428 ret |= regmap_field_write(phy->fields[AHB_PMA_LN_GEN3_AGC_SD_THSEL], 0x83);
429 ret |= regmap_field_write(phy->fields[AHB_PMA_LN_RX_SELR_GEN3], 0x81);
430 ret |= regmap_field_write(phy->fields[AHB_PMA_LN_TX_DRV], 0x3b);
431 ret |= regmap_field_write(phy->fields[P2S_RBUF_PTR_DIFF], 0x3);
432 ret |= regmap_field_write(phy->fields[CONFIG_VERSION], VERSION_VAL);
433 ret |= regmap_field_write(phy->fields[COMRXEQ_MS_INIT_CTRL_7_0], 0xf);
434 ret |= regmap_field_write(phy->fields[COMRXEQ_HS_INIT_CAL_7_0], 0x4f);
435 ret |= regmap_field_write(phy->fields[COMRXEQ_MS_RECAL_CTRL_7_0], 0xf);
436 ret |= regmap_field_write(phy->fields[COMRXEQ_HS_RECAL_CTRL_7_0], 0x4f);
437 ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_ATT_CONFIG], 0x7);
438 ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_EBSTADAPT_WIN_LEN], 0x7f);
439 ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_3_4], 0xf);
440 ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_14_15_16], 0x9a);
441 ret |= regmap_field_write(phy->fields[COMRXEQ_CSR_DLEV_ERR_THRESH], 0x32);
442 ret |= regmap_field_write(phy->fields[COMRXEQ_CTRL_25], 0x80);
443 ret |= regmap_field_write(phy->fields[CSR_RXEQ_RATE_CHANGE_CAL_RUN_RATE2_O], 0xf);
444 ret |= regmap_field_write(phy->fields[COMRXEQ_HS_RCHANGE_CTRL_7_0], 0x4f);
445 ret |= regmap_field_write(phy->fields[CMU_MASTER_CDN], 0x1);
446 ret |= regmap_field_write(phy->fields[L1_MASTER_CDN], 0x2);
476 ret |= regmap_field_write(phy->fields[POR_EN], 0x1);
480 ret |= regmap_field_write(phy->fields[POR_EN], 0x0);
740 am654_phy->fields[i] = devm_regmap_field_alloc(dev,
743 if (IS_ERR(am654_phy->fields[i])) {
745 return PTR_ERR(am654_phy->fields[i]);