Lines Matching refs:index
794 unsigned int index, bool idle)
798 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
813 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index));
819 unsigned int index, bool enable)
825 port = tegra_xusb_find_port(padctl, "usb3", index);
832 offset = XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL1(lane->index);
880 unsigned int index)
890 usb2->base.soc = &pad->soc->lanes[index];
891 usb2->base.index = index;
1003 lane->index);
1044 unsigned int index = lane->index;
1048 port = tegra_xusb_find_usb2_port(padctl, index);
1050 dev_err(&phy->dev, "no port found for USB2 lane %u\n", index);
1061 port->usb3_port_fake, index);
1100 value &= ~XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_MASK(index);
1102 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DISABLED(index);
1104 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_DEVICE(index);
1106 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_HOST(index);
1108 value |= XUSB_PADCTL_USB2_PORT_CAP_PORTX_CAP_OTG(index);
1111 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
1117 value |= (priv->fuse.hs_curr_level[index] +
1120 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
1122 value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
1134 padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
1137 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
1147 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL1(index));
1211 port = tegra_xusb_find_usb2_port(padctl, lane->index);
1214 lane->index);
1345 unsigned int index)
1355 hsic->base.soc = &pad->soc->lanes[index];
1356 hsic->base.index = index;
1410 unsigned int index = lane->index;
1421 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL1(index));
1426 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
1428 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL2(index));
1437 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL2(index));
1439 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
1455 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL0(index));
1494 unsigned int index = lane->index;
1497 value = padctl_readl(padctl, XUSB_PADCTL_HSIC_PADX_CTL0(index));
1507 padctl_writel(padctl, value, XUSB_PADCTL_HSIC_PADX_CTL1(index));
1604 unsigned int index)
1614 pcie->base.soc = &pad->soc->lanes[index];
1615 pcie->base.index = index;
1668 value |= XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index);
1683 value &= ~XUSB_PADCTL_USB3_PAD_MUX_PCIE_IDDQ_DISABLE(lane->index);
1775 unsigned int index)
1785 sata->base.soc = &pad->soc->lanes[index];
1786 sata->base.index = index;
1839 value |= XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index);
1854 value &= ~XUSB_PADCTL_USB3_PAD_MUX_SATA_IDDQ_DISABLE(lane->index);
1952 return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
1975 return tegra_xusb_find_lane(port->padctl, "hsic", port->index);
1990 unsigned int index = port->index;
1997 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);
1999 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(index);
2001 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index);
2002 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, usb3->port);
2014 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));
2019 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL1(index));
2021 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));
2026 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL2(index));
2029 XUSB_PADCTL_UPHY_USB3_PADX_ECTL3(index));
2031 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));
2036 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_USB3_PADX_ECTL4(index));
2039 XUSB_PADCTL_UPHY_USB3_PADX_ECTL6(index));
2053 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);
2059 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);
2065 value &= ~XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);
2076 unsigned int index = port->index;
2080 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN_EARLY(index);
2086 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_CLAMP_EN(index);
2092 value |= XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(index);
2103 value &= ~XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP_MASK(index);
2104 value |= XUSB_PADCTL_SS_PORT_MAP_PORTX_MAP(index, 0x7);
2142 XUSB_PADCTL_USB2_BATTERY_CHRG_OTGPADX_CTL0(lane->index));