Lines Matching defs:miphy_phy
365 static inline void miphy28lp_set_reset(struct miphy28lp_phy *miphy_phy)
367 void __iomem *base = miphy_phy->base;
379 if (miphy_phy->type == PHY_TYPE_PCIE) {
388 static inline void miphy28lp_pll_calibration(struct miphy28lp_phy *miphy_phy,
391 void __iomem *base = miphy_phy->base;
412 if (miphy_phy->type != PHY_TYPE_SATA)
417 if (miphy_phy->type == PHY_TYPE_USB3) {
430 static inline void miphy28lp_sata_config_gen(struct miphy28lp_phy *miphy_phy)
432 void __iomem *base = miphy_phy->base;
457 static inline void miphy28lp_pcie_config_gen(struct miphy28lp_phy *miphy_phy)
459 void __iomem *base = miphy_phy->base;
486 static inline int miphy28lp_wait_compensation(struct miphy28lp_phy *miphy_phy)
491 return readb_relaxed_poll_timeout(miphy_phy->base + MIPHY_COMP_FSM_6,
496 static inline int miphy28lp_compensation(struct miphy28lp_phy *miphy_phy,
499 void __iomem *base = miphy_phy->base;
509 if (miphy_phy->type == PHY_TYPE_PCIE)
519 if (miphy_phy->type == PHY_TYPE_PCIE)
520 return miphy28lp_wait_compensation(miphy_phy);
525 static inline void miphy28_usb3_miphy_reset(struct miphy28lp_phy *miphy_phy)
527 void __iomem *base = miphy_phy->base;
553 static void miphy_sata_tune_ssc(struct miphy28lp_phy *miphy_phy)
555 void __iomem *base = miphy_phy->base;
591 static void miphy_pcie_tune_ssc(struct miphy28lp_phy *miphy_phy)
593 void __iomem *base = miphy_phy->base;
631 static inline void miphy_tune_tx_impedance(struct miphy28lp_phy *miphy_phy)
634 writeb_relaxed(0x02, miphy_phy->base + MIPHY_COMP_POSTP);
637 static inline int miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy)
639 void __iomem *base = miphy_phy->base;
644 miphy28lp_set_reset(miphy_phy);
647 miphy28lp_pll_calibration(miphy_phy, &sata_pll_ratio);
650 miphy28lp_sata_config_gen(miphy_phy);
661 err = miphy28lp_compensation(miphy_phy, &sata_pll_ratio);
665 if (miphy_phy->px_rx_pol_inv) {
667 val = readb_relaxed(miphy_phy->base + MIPHY_CONTROL);
669 writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL);
672 if (miphy_phy->ssc)
673 miphy_sata_tune_ssc(miphy_phy);
675 if (miphy_phy->tx_impedance)
676 miphy_tune_tx_impedance(miphy_phy);
681 static inline int miphy28lp_configure_pcie(struct miphy28lp_phy *miphy_phy)
683 void __iomem *base = miphy_phy->base;
687 miphy28lp_set_reset(miphy_phy);
690 miphy28lp_pll_calibration(miphy_phy, &pcie_pll_ratio);
693 miphy28lp_pcie_config_gen(miphy_phy);
704 err = miphy28lp_compensation(miphy_phy, &pcie_pll_ratio);
708 if (miphy_phy->ssc)
709 miphy_pcie_tune_ssc(miphy_phy);
711 if (miphy_phy->tx_impedance)
712 miphy_tune_tx_impedance(miphy_phy);
718 static inline void miphy28lp_configure_usb3(struct miphy28lp_phy *miphy_phy)
720 void __iomem *base = miphy_phy->base;
724 miphy28lp_set_reset(miphy_phy);
727 miphy28lp_pll_calibration(miphy_phy, &usb3_pll_ratio);
796 miphy28_usb3_miphy_reset(miphy_phy);
799 static inline int miphy_is_ready(struct miphy28lp_phy *miphy_phy)
808 if (miphy_phy->type == PHY_TYPE_SATA)
811 return readb_relaxed_poll_timeout(miphy_phy->base + MIPHY_STATUS_1,
816 static int miphy_osc_is_ready(struct miphy28lp_phy *miphy_phy)
818 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
821 if (!miphy_phy->osc_rdy)
824 if (!miphy_phy->syscfg_reg[SYSCFG_STATUS])
828 miphy_phy->syscfg_reg[SYSCFG_STATUS],
866 static int miphy28lp_setup(struct miphy28lp_phy *miphy_phy, u32 miphy_val)
869 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
871 if (!miphy_phy->syscfg_reg[SYSCFG_CTRL])
874 err = reset_control_assert(miphy_phy->miphy_rst);
880 if (miphy_phy->osc_force_ext)
884 miphy_phy->syscfg_reg[SYSCFG_CTRL],
887 err = reset_control_deassert(miphy_phy->miphy_rst);
893 return miphy_osc_is_ready(miphy_phy);
896 static int miphy28lp_init_sata(struct miphy28lp_phy *miphy_phy)
898 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
901 if ((!miphy_phy->syscfg_reg[SYSCFG_SATA]) ||
902 (!miphy_phy->syscfg_reg[SYSCFG_PCI]) ||
903 (!miphy_phy->base))
906 dev_info(miphy_dev->dev, "sata-up mode, addr 0x%p\n", miphy_phy->base);
909 sata_conf |= ((miphy_phy->sata_gen - SATA_GEN1) << SATA_SPDMODE);
912 miphy_phy->syscfg_reg[SYSCFG_SATA],
915 regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_reg[SYSCFG_PCI],
919 err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT);
927 miphy28lp_configure_sata(miphy_phy);
929 return miphy_is_ready(miphy_phy);
932 static int miphy28lp_init_pcie(struct miphy28lp_phy *miphy_phy)
934 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
937 if ((!miphy_phy->syscfg_reg[SYSCFG_SATA]) ||
938 (!miphy_phy->syscfg_reg[SYSCFG_PCI])
939 || (!miphy_phy->base) || (!miphy_phy->pipebase))
942 dev_info(miphy_dev->dev, "pcie-up mode, addr 0x%p\n", miphy_phy->base);
946 miphy_phy->syscfg_reg[SYSCFG_SATA],
949 regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_reg[SYSCFG_PCI],
953 err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT);
961 err = miphy28lp_configure_pcie(miphy_phy);
966 writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */
967 writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */
968 writeb_relaxed(0x68, miphy_phy->pipebase + 0x108); /* Fall_0 */
969 writeb_relaxed(0x61, miphy_phy->pipebase + 0x109); /* Fall-1 */
970 writeb_relaxed(0x68, miphy_phy->pipebase + 0x10c); /* Threshold_0 */
971 writeb_relaxed(0x60, miphy_phy->pipebase + 0x10d); /* Threshold_1 */
974 return miphy_is_ready(miphy_phy);
977 static int miphy28lp_init_usb3(struct miphy28lp_phy *miphy_phy)
979 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
982 if ((!miphy_phy->base) || (!miphy_phy->pipebase))
985 dev_info(miphy_dev->dev, "usb3-up mode, addr 0x%p\n", miphy_phy->base);
988 err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_SYNC_D_EN);
995 miphy28lp_configure_usb3(miphy_phy);
998 writeb_relaxed(0x68, miphy_phy->pipebase + 0x23);
999 writeb_relaxed(0x61, miphy_phy->pipebase + 0x24);
1000 writeb_relaxed(0x68, miphy_phy->pipebase + 0x26);
1001 writeb_relaxed(0x61, miphy_phy->pipebase + 0x27);
1002 writeb_relaxed(0x18, miphy_phy->pipebase + 0x29);
1003 writeb_relaxed(0x61, miphy_phy->pipebase + 0x2a);
1006 writeb_relaxed(0X67, miphy_phy->pipebase + 0x68);
1007 writeb_relaxed(0x0d, miphy_phy->pipebase + 0x69);
1008 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6a);
1009 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6b);
1010 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6c);
1011 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6d);
1012 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6e);
1013 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6f);
1015 return miphy_is_ready(miphy_phy);
1020 struct miphy28lp_phy *miphy_phy = phy_get_drvdata(phy);
1021 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
1026 switch (miphy_phy->type) {
1029 ret = miphy28lp_init_sata(miphy_phy);
1032 ret = miphy28lp_init_pcie(miphy_phy);
1035 ret = miphy28lp_init_usb3(miphy_phy);
1047 static int miphy28lp_get_addr(struct miphy28lp_phy *miphy_phy)
1049 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
1050 struct device_node *phynode = miphy_phy->phy->dev.of_node;
1053 if ((miphy_phy->type != PHY_TYPE_SATA) &&
1054 (miphy_phy->type != PHY_TYPE_PCIE) &&
1055 (miphy_phy->type != PHY_TYPE_USB3)) {
1060 PHY_TYPE_name[miphy_phy->type - PHY_TYPE_SATA],
1061 &miphy_phy->base);
1065 if ((miphy_phy->type == PHY_TYPE_PCIE) ||
1066 (miphy_phy->type == PHY_TYPE_USB3)) {
1068 &miphy_phy->pipebase);
1080 struct miphy28lp_phy *miphy_phy = NULL;
1091 miphy_phy = miphy_dev->phys[index];
1095 if (!miphy_phy) {
1100 miphy_phy->type = args->args[0];
1102 ret = miphy28lp_get_addr(miphy_phy);
1106 return miphy_phy->phy;
1115 struct miphy28lp_phy *miphy_phy)
1117 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev;
1120 miphy_phy->miphy_rst =
1123 if (IS_ERR(miphy_phy->miphy_rst)) {
1126 return PTR_ERR(miphy_phy->miphy_rst);
1129 err = reset_control_deassert(miphy_phy->miphy_rst);
1139 struct miphy28lp_phy *miphy_phy)
1144 miphy_phy->osc_force_ext =
1147 miphy_phy->osc_rdy = of_property_read_bool(np, "st,osc-rdy");
1149 miphy_phy->px_rx_pol_inv =
1152 miphy_phy->ssc = of_property_read_bool(np, "st,ssc-on");
1154 miphy_phy->tx_impedance =
1157 of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen);
1158 if (!miphy_phy->sata_gen)
1159 miphy_phy->sata_gen = SATA_GEN1;
1163 miphy_phy->syscfg_reg[i] = ctrlreg;
1200 struct miphy28lp_phy *miphy_phy;
1202 miphy_phy = devm_kzalloc(&pdev->dev, sizeof(*miphy_phy),
1204 if (!miphy_phy) {
1209 miphy_dev->phys[port] = miphy_phy;
1221 ret = miphy28lp_of_probe(child, miphy_phy);