Lines Matching refs:otg
201 u32 otg;
214 otg = readl(drv->reg_phy + EXYNOS_5250_USBOTGSYS);
216 otg &= ~EXYNOS_5250_USBOTGSYS_FSEL_MASK;
217 otg |= drv->ref_reg_val << EXYNOS_5250_USBOTGSYS_FSEL_SHIFT;
219 otg &= ~(EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND |
222 otg |= EXYNOS_5250_USBOTGSYS_PHY_SW_RST |
227 otg &= ~EXYNOS_5250_USBOTGSYS_REFCLKSEL_MASK;
228 otg |= EXYNOS_5250_REFCLKSEL_CLKCORE <<
230 writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
232 otg &= ~(EXYNOS_5250_USBOTGSYS_PHY_SW_RST |
236 writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
266 otg = readl(drv->reg_phy + EXYNOS_5250_USBOTGSYS);
268 otg &= ~EXYNOS_5250_USBOTGSYS_FSEL_MASK;
269 otg |= drv->ref_reg_val << EXYNOS_5250_USBOTGSYS_FSEL_SHIFT;
271 otg &= ~(EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND |
274 otg |= EXYNOS_5250_USBOTGSYS_PHY_SW_RST |
279 otg &= ~EXYNOS_5250_USBOTGSYS_REFCLKSEL_MASK;
280 otg |= EXYNOS_5250_REFCLKSEL_CLKCORE <<
282 writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);
284 otg &= ~(EXYNOS_5250_USBOTGSYS_PHY_SW_RST |
327 u32 otg;
334 otg = readl(drv->reg_phy + EXYNOS_5250_USBOTGSYS);
335 otg |= (EXYNOS_5250_USBOTGSYS_FORCE_SUSPEND |
338 writel(otg, drv->reg_phy + EXYNOS_5250_USBOTGSYS);