Lines Matching refs:val
89 u32 val = 0;
99 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
101 val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
102 val |= RESET_GLOBAL_RST_N | RESET_CMN_RST_N | RESET_CMN_BLOCK_RST_N
105 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
107 val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
108 val |= LINK_RESET;
109 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
111 val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
112 val |= RESET_CMN_RST_N;
113 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
115 val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
116 val &= ~PHCTRLM_REF_RATE;
117 writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
120 val = readl(sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
121 val |= PHCTRLM_HIGH_SPEED;
122 writel(val, sata_phy->regs + EXYNOS5_SATA_PHSATA_CTRLM);
124 val = readl(sata_phy->regs + EXYNOS5_SATA_CTRL0);
125 val |= CTRL0_P0_PHY_CALIBRATED_SEL | CTRL0_P0_PHY_CALIBRATED;
126 writel(val, sata_phy->regs + EXYNOS5_SATA_CTRL0);
128 val = readl(sata_phy->regs + EXYNOS5_SATA_MODE0);
129 val |= SATA_SPD_GEN3;
130 writel(val, sata_phy->regs + EXYNOS5_SATA_MODE0);
137 val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
138 val &= ~RESET_CMN_RST_N;
139 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);
141 val = readl(sata_phy->regs + EXYNOS5_SATA_RESET);
142 val |= RESET_CMN_RST_N;
143 writel(val, sata_phy->regs + EXYNOS5_SATA_RESET);