Lines Matching defs:phy_drd
164 void (*phy_init)(struct exynos5_usbdrd_phy *phy_drd);
281 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
284 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
294 switch (phy_drd->extrefclk) {
312 dev_dbg(phy_drd->dev, "unsupported ref clk\n");
327 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
330 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
338 reg |= PHYCLKRST_FSEL(phy_drd->extrefclk);
343 static void exynos5_usbdrd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd)
347 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
351 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
353 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
355 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
358 static void exynos5_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
362 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
366 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
368 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
372 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1);
375 writel(PHYUTMI_OTGDISABLE, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
377 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
379 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
387 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
389 ret = clk_prepare_enable(phy_drd->clk);
394 writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
395 writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYRESUME);
403 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM);
405 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
408 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0);
411 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL);
413 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL);
416 inst->phy_cfg->phy_init(phy_drd);
432 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
437 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
439 clk_disable_unprepare(phy_drd->clk);
449 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
451 ret = clk_prepare_enable(phy_drd->clk);
458 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI);
461 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
465 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST);
468 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
471 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST);
473 clk_disable_unprepare(phy_drd->clk);
482 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
484 dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n");
486 clk_prepare_enable(phy_drd->ref_clk);
487 if (!phy_drd->drv_data->has_common_clk_gate) {
488 clk_prepare_enable(phy_drd->pipeclk);
489 clk_prepare_enable(phy_drd->utmiclk);
490 clk_prepare_enable(phy_drd->itpclk);
494 if (phy_drd->vbus_boost) {
495 ret = regulator_enable(phy_drd->vbus_boost);
497 dev_err(phy_drd->dev,
503 if (phy_drd->vbus) {
504 ret = regulator_enable(phy_drd->vbus);
506 dev_err(phy_drd->dev, "Failed to enable VBUS supply\n");
517 if (phy_drd->vbus_boost)
518 regulator_disable(phy_drd->vbus_boost);
521 clk_disable_unprepare(phy_drd->ref_clk);
522 if (!phy_drd->drv_data->has_common_clk_gate) {
523 clk_disable_unprepare(phy_drd->itpclk);
524 clk_disable_unprepare(phy_drd->utmiclk);
525 clk_disable_unprepare(phy_drd->pipeclk);
534 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
536 dev_dbg(phy_drd->dev, "Request to power_off usbdrd_phy phy\n");
542 if (phy_drd->vbus)
543 regulator_disable(phy_drd->vbus);
544 if (phy_drd->vbus_boost)
545 regulator_disable(phy_drd->vbus_boost);
547 clk_disable_unprepare(phy_drd->ref_clk);
548 if (!phy_drd->drv_data->has_common_clk_gate) {
549 clk_disable_unprepare(phy_drd->itpclk);
550 clk_disable_unprepare(phy_drd->pipeclk);
551 clk_disable_unprepare(phy_drd->utmiclk);
557 static int crport_handshake(struct exynos5_usbdrd_phy *phy_drd,
563 writel(val | cmd, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
565 err = readl_poll_timeout(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1,
568 dev_err(phy_drd->dev, "CRPORT handshake timeout1 (0x%08x)\n", val);
572 writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
574 err = readl_poll_timeout(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1,
577 dev_err(phy_drd->dev, "CRPORT handshake timeout2 (0x%08x)\n", val);
584 static int crport_ctrl_write(struct exynos5_usbdrd_phy *phy_drd,
591 phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
592 ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(addr),
599 phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0);
600 ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data),
605 ret = crport_handshake(phy_drd, PHYREG0_CR_DATA_IN(data),
616 static int exynos5420_usbdrd_phy_calibrate(struct exynos5_usbdrd_phy *phy_drd)
630 ret = crport_ctrl_write(phy_drd,
634 dev_err(phy_drd->dev,
644 ret = crport_ctrl_write(phy_drd,
648 dev_err(phy_drd->dev,
662 switch (phy_drd->extrefclk) {
676 ret = crport_ctrl_write(phy_drd,
680 dev_err(phy_drd->dev,
689 struct exynos5_usbdrd_phy *phy_drd = dev_get_drvdata(dev);
694 return phy_drd->phys[args->args[0]].phy;
700 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst);
703 return exynos5420_usbdrd_phy_calibrate(phy_drd);
716 static int exynos5_usbdrd_phy_clk_handle(struct exynos5_usbdrd_phy *phy_drd)
721 phy_drd->clk = devm_clk_get(phy_drd->dev, "phy");
722 if (IS_ERR(phy_drd->clk)) {
723 dev_err(phy_drd->dev, "Failed to get phy clock\n");
724 return PTR_ERR(phy_drd->clk);
727 phy_drd->ref_clk = devm_clk_get(phy_drd->dev, "ref");
728 if (IS_ERR(phy_drd->ref_clk)) {
729 dev_err(phy_drd->dev, "Failed to get phy reference clock\n");
730 return PTR_ERR(phy_drd->ref_clk);
732 ref_rate = clk_get_rate(phy_drd->ref_clk);
734 ret = exynos5_rate_to_clk(ref_rate, &phy_drd->extrefclk);
736 dev_err(phy_drd->dev, "Clock rate (%ld) not supported\n",
741 if (!phy_drd->drv_data->has_common_clk_gate) {
742 phy_drd->pipeclk = devm_clk_get(phy_drd->dev, "phy_pipe");
743 if (IS_ERR(phy_drd->pipeclk)) {
744 dev_info(phy_drd->dev,
746 phy_drd->pipeclk = NULL;
749 phy_drd->utmiclk = devm_clk_get(phy_drd->dev, "phy_utmi");
750 if (IS_ERR(phy_drd->utmiclk)) {
751 dev_info(phy_drd->dev,
753 phy_drd->utmiclk = NULL;
756 phy_drd->itpclk = devm_clk_get(phy_drd->dev, "itp");
757 if (IS_ERR(phy_drd->itpclk)) {
758 dev_info(phy_drd->dev,
760 phy_drd->itpclk = NULL;
830 struct exynos5_usbdrd_phy *phy_drd;
839 phy_drd = devm_kzalloc(dev, sizeof(*phy_drd), GFP_KERNEL);
840 if (!phy_drd)
843 dev_set_drvdata(dev, phy_drd);
844 phy_drd->dev = dev;
847 phy_drd->reg_phy = devm_ioremap_resource(dev, res);
848 if (IS_ERR(phy_drd->reg_phy))
849 return PTR_ERR(phy_drd->reg_phy);
855 phy_drd->drv_data = drv_data;
857 ret = exynos5_usbdrd_phy_clk_handle(phy_drd);
881 pmu_offset = phy_drd->drv_data->pmu_offset_usbdrd1_phy;
885 pmu_offset = phy_drd->drv_data->pmu_offset_usbdrd0_phy;
890 phy_drd->vbus = devm_regulator_get(dev, "vbus");
891 if (IS_ERR(phy_drd->vbus)) {
892 ret = PTR_ERR(phy_drd->vbus);
897 phy_drd->vbus = NULL;
900 phy_drd->vbus_boost = devm_regulator_get(dev, "vbus-boost");
901 if (IS_ERR(phy_drd->vbus_boost)) {
902 ret = PTR_ERR(phy_drd->vbus_boost);
907 phy_drd->vbus_boost = NULL;
920 phy_drd->phys[i].phy = phy;
921 phy_drd->phys[i].index = i;
922 phy_drd->phys[i].reg_pmu = reg_pmu;
923 phy_drd->phys[i].pmu_offset = pmu_offset;
924 phy_drd->phys[i].phy_cfg = &drv_data->phy_cfg[i];
925 phy_set_drvdata(phy, &phy_drd->phys[i]);
931 dev_err(phy_drd->dev, "Failed to register phy provider\n");