Lines Matching refs:port_cfg
171 * @port_cfg: port register configuration, assigned by driver data.
188 const struct rockchip_usb2phy_port_cfg *port_cfg;
416 &rport->port_cfg->bvalid_det_clr,
422 &rport->port_cfg->bvalid_det_en,
436 &rport->port_cfg->ls_det_clr, true);
441 &rport->port_cfg->ls_det_en, true);
469 ret = property_enable(base, &rport->port_cfg->phy_sus, false);
494 ret = property_enable(base, &rport->port_cfg->phy_sus, true);
538 &rport->port_cfg->utmi_bvalid);
796 unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
797 rport->port_cfg->utmi_hstdet.bitstart + 1;
804 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
808 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd);
812 uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
813 rport->port_cfg->utmi_hstdet.bitstart);
814 ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
815 rport->port_cfg->utmi_ls.bitstart);
818 state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
819 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
862 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
863 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, true);
886 if (!property_enabled(rphy->grf, &rport->port_cfg->ls_det_st))
892 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, false);
893 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
913 if (!property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st))
919 property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true);
933 if (property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st))
946 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
988 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];