Lines Matching refs:phy_cfg
207 * @phy_cfg: phy register configuration, assigned by driver data.
221 const struct rockchip_usb2phy_cfg *phy_cfg;
265 if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) {
266 ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true);
284 property_enable(base, &rphy->phy_cfg->clkout_ctl, false);
293 return property_enabled(base, &rphy->phy_cfg->clkout_ctl);
660 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
661 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en);
669 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en);
670 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en);
678 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en);
679 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en);
702 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false);
712 &rphy->phy_cfg->chg_det.dp_det);
730 &rphy->phy_cfg->chg_det.cp_det);
752 &rphy->phy_cfg->chg_det.dcp_det);
766 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true);
946 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
988 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
1123 rphy->phy_cfg = &phy_cfgs[index];
1130 if (!rphy->phy_cfg) {
1185 if (++index >= rphy->phy_cfg->num_ports)