Lines Matching refs:inno
280 int (*init)(struct inno_hdmi_phy *inno);
281 int (*power_on)(struct inno_hdmi_phy *inno,
284 void (*power_off)(struct inno_hdmi_phy *inno);
382 static inline void inno_write(struct inno_hdmi_phy *inno, u32 reg, u8 val)
384 regmap_write(inno->regmap, reg * 4, val);
387 static inline u8 inno_read(struct inno_hdmi_phy *inno, u32 reg)
391 regmap_read(inno->regmap, reg * 4, &val);
396 static inline void inno_update_bits(struct inno_hdmi_phy *inno, u8 reg,
399 regmap_update_bits(inno->regmap, reg * 4, mask, val);
402 #define inno_poll(inno, reg, val, cond, sleep_us, timeout_us) \
403 regmap_read_poll_timeout((inno)->regmap, (reg) * 4, val, cond, \
406 static unsigned long inno_hdmi_phy_get_tmdsclk(struct inno_hdmi_phy *inno,
409 int bus_width = phy_get_bus_width(inno->phy);
426 struct inno_hdmi_phy *inno = dev_id;
429 intr_stat1 = inno_read(inno, 0x04);
430 intr_stat2 = inno_read(inno, 0x06);
431 intr_stat3 = inno_read(inno, 0x08);
434 inno_write(inno, 0x04, intr_stat1);
436 inno_write(inno, 0x06, intr_stat2);
438 inno_write(inno, 0x08, intr_stat3);
448 struct inno_hdmi_phy *inno = dev_id;
450 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, 0);
452 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, RK3328_PDATA_EN);
459 struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
461 const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table;
462 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno,
463 inno->pixclock);
467 dev_err(inno->dev, "TMDS clock is zero!\n");
471 if (!inno->plat_data->ops->power_on)
476 cfg->version & inno->chip_version)
486 dev_dbg(inno->dev, "Inno HDMI PHY Power On\n");
488 ret = clk_prepare_enable(inno->phyclk);
492 ret = inno->plat_data->ops->power_on(inno, cfg, phy_cfg);
494 clk_disable_unprepare(inno->phyclk);
503 struct inno_hdmi_phy *inno = phy_get_drvdata(phy);
505 if (!inno->plat_data->ops->power_off)
508 inno->plat_data->ops->power_off(inno);
510 clk_disable_unprepare(inno->phyclk);
512 dev_dbg(inno->dev, "Inno HDMI PHY Power Off\n");
524 struct pre_pll_config *inno_hdmi_phy_get_pre_pll_cfg(struct inno_hdmi_phy *inno,
528 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
542 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
545 status = inno_read(inno, 0xe0) & RK3228_PRE_PLL_POWER_DOWN;
551 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
553 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, 0);
559 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
561 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN,
569 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
574 nd = inno_read(inno, 0xe2) & RK3228_PRE_PLL_PRE_DIV_MASK;
575 nf = (inno_read(inno, 0xe2) & RK3228_PRE_PLL_FB_DIV_8_MASK) << 1;
576 nf |= inno_read(inno, 0xe3);
579 if (inno_read(inno, 0xe2) & RK3228_PCLK_VCO_DIV_5_MASK) {
582 no_a = inno_read(inno, 0xe4) & RK3228_PRE_PLL_PCLK_DIV_A_MASK;
585 no_b = inno_read(inno, 0xe4) & RK3228_PRE_PLL_PCLK_DIV_B_MASK;
588 no_d = inno_read(inno, 0xe5) & RK3228_PRE_PLL_PCLK_DIV_D_MASK;
593 inno->pixclock = vco;
595 dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
622 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
624 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
628 dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
631 cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
636 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN,
639 inno_update_bits(inno, 0xe2, RK3228_PRE_PLL_FB_DIV_8_MASK |
645 inno_write(inno, 0xe3, RK3228_PRE_PLL_FB_DIV_7_0(cfg->fbdiv));
646 inno_update_bits(inno, 0xe4, RK3228_PRE_PLL_PCLK_DIV_B_MASK |
650 inno_update_bits(inno, 0xe5, RK3228_PRE_PLL_PCLK_DIV_C_MASK |
654 inno_update_bits(inno, 0xe6, RK3228_PRE_PLL_TMDSCLK_DIV_C_MASK |
662 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN, 0);
665 ret = inno_poll(inno, 0xe8, v, v & RK3228_PRE_PLL_LOCK_STATUS,
668 dev_err(inno->dev, "Pre-PLL locking failed\n");
672 inno->pixclock = rate;
688 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
691 status = inno_read(inno, 0xa0) & RK3328_PRE_PLL_POWER_DOWN;
697 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
699 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0);
705 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
707 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN,
715 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
721 nd = inno_read(inno, 0xa1) & RK3328_PRE_PLL_PRE_DIV_MASK;
722 nf = ((inno_read(inno, 0xa2) & RK3328_PRE_PLL_FB_DIV_11_8_MASK) << 8);
723 nf |= inno_read(inno, 0xa3);
726 if (!(inno_read(inno, 0xa2) & RK3328_PRE_PLL_FRAC_DIV_DISABLE)) {
727 frac = inno_read(inno, 0xd3) |
728 (inno_read(inno, 0xd2) << 8) |
729 (inno_read(inno, 0xd1) << 16);
733 if (inno_read(inno, 0xa0) & RK3328_PCLK_VCO_DIV_5_MASK) {
736 no_a = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_A_MASK;
737 no_b = inno_read(inno, 0xa5) & RK3328_PRE_PLL_PCLK_DIV_B_MASK;
740 no_c = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_C_MASK;
743 no_d = inno_read(inno, 0xa6) & RK3328_PRE_PLL_PCLK_DIV_D_MASK;
748 inno->pixclock = DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000;
750 dev_dbg(inno->dev, "%s rate %lu vco %llu\n",
751 __func__, inno->pixclock, vco);
753 return inno->pixclock;
778 struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
780 unsigned long tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
784 dev_dbg(inno->dev, "%s rate %lu tmdsclk %lu\n",
787 cfg = inno_hdmi_phy_get_pre_pll_cfg(inno, rate);
791 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN,
795 inno_update_bits(inno, 0xa0, RK3328_PCLK_VCO_DIV_5_MASK,
797 inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv));
802 inno_write(inno, 0xa2, RK3328_PRE_PLL_FB_DIV_11_8(cfg->fbdiv) | val);
803 inno_write(inno, 0xa3, RK3328_PRE_PLL_FB_DIV_7_0(cfg->fbdiv));
804 inno_write(inno, 0xa5, RK3328_PRE_PLL_PCLK_DIV_A(cfg->pclk_div_a) |
806 inno_write(inno, 0xa6, RK3328_PRE_PLL_PCLK_DIV_C(cfg->pclk_div_c) |
808 inno_write(inno, 0xa4, RK3328_PRE_PLL_TMDSCLK_DIV_C(cfg->tmds_div_c) |
811 inno_write(inno, 0xd3, RK3328_PRE_PLL_FRAC_DIV_7_0(cfg->fracdiv));
812 inno_write(inno, 0xd2, RK3328_PRE_PLL_FRAC_DIV_15_8(cfg->fracdiv));
813 inno_write(inno, 0xd1, RK3328_PRE_PLL_FRAC_DIV_23_16(cfg->fracdiv));
815 inno_update_bits(inno, 0xa0, RK3328_PRE_PLL_POWER_DOWN, 0);
818 ret = inno_poll(inno, 0xa9, val, val & RK3328_PRE_PLL_LOCK_STATUS,
821 dev_err(inno->dev, "Pre-PLL locking failed\n");
825 inno->pixclock = rate;
839 static int inno_hdmi_phy_clk_register(struct inno_hdmi_phy *inno)
841 struct device *dev = inno->dev;
847 parent_name = __clk_get_name(inno->refoclk);
853 init.ops = inno->plat_data->clk_ops;
858 inno->hw.init = &init;
860 inno->phyclk = devm_clk_register(dev, &inno->hw);
861 if (IS_ERR(inno->phyclk)) {
862 ret = PTR_ERR(inno->phyclk);
867 ret = of_clk_add_provider(np, of_clk_src_simple_get, inno->phyclk);
876 static int inno_hdmi_phy_rk3228_init(struct inno_hdmi_phy *inno)
882 inno_write(inno, 0x01, RK3228_BYPASS_RXSENSE_EN |
885 inno_update_bits(inno, 0x02, RK3228_BYPASS_PDATA_EN,
889 inno_update_bits(inno, 0xaa, RK3228_POST_PLL_CTRL_MANUAL,
892 inno->chip_version = 1;
898 inno_hdmi_phy_rk3228_power_on(struct inno_hdmi_phy *inno,
905 inno_update_bits(inno, 0x02, RK3228_PDATAEN_DISABLE,
907 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN |
913 inno_update_bits(inno, 0xe9, RK3228_POST_PLL_PRE_DIV_MASK,
915 inno_update_bits(inno, 0xeb, RK3228_POST_PLL_FB_DIV_8_MASK,
917 inno_write(inno, 0xea, RK3228_POST_PLL_FB_DIV_7_0(cfg->fbdiv));
920 inno_update_bits(inno, 0xe9, RK3228_POST_PLL_POST_DIV_ENABLE,
925 inno_update_bits(inno, 0xe9, RK3228_POST_PLL_POST_DIV_ENABLE,
927 inno_update_bits(inno, 0xeb, RK3228_POST_PLL_POST_DIV_MASK,
932 inno_write(inno, 0xef + v, phy_cfg->regs[v]);
934 inno_update_bits(inno, 0xe0, RK3228_PRE_PLL_POWER_DOWN |
936 inno_update_bits(inno, 0xe1, RK3228_BANDGAP_ENABLE,
938 inno_update_bits(inno, 0xe1, RK3228_TMDS_DRIVER_ENABLE,
942 ret = inno_poll(inno, 0xeb, v, v & RK3228_POST_PLL_LOCK_STATUS,
945 dev_err(inno->dev, "Post-PLL locking failed\n");
952 inno_update_bits(inno, 0x02, RK3228_PDATAEN_DISABLE, 0);
956 static void inno_hdmi_phy_rk3228_power_off(struct inno_hdmi_phy *inno)
958 inno_update_bits(inno, 0xe1, RK3228_TMDS_DRIVER_ENABLE, 0);
959 inno_update_bits(inno, 0xe1, RK3228_BANDGAP_ENABLE, 0);
960 inno_update_bits(inno, 0xe0, RK3228_POST_PLL_POWER_DOWN,
970 static int inno_hdmi_phy_rk3328_init(struct inno_hdmi_phy *inno)
980 inno_write(inno, 0x01, RK3328_BYPASS_RXSENSE_EN |
983 inno_write(inno, 0x02, RK3328_INT_POL_HIGH | RK3328_BYPASS_PDATA_EN |
987 inno_write(inno, 0x05, 0);
988 inno_write(inno, 0x07, 0);
991 inno->chip_version = 1;
992 cell = nvmem_cell_get(inno->dev, "cpu-version");
1006 inno->chip_version = efuse_buf[0] + 1;
1013 inno_hdmi_phy_rk3328_power_on(struct inno_hdmi_phy *inno,
1020 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, 0);
1021 inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN,
1024 inno_write(inno, 0xac, RK3328_POST_PLL_FB_DIV_7_0(cfg->fbdiv));
1026 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
1028 inno_write(inno, 0xaa, RK3328_POST_PLL_REFCLK_SEL_TMDS |
1033 inno_write(inno, 0xad, v);
1034 inno_write(inno, 0xab, RK3328_POST_PLL_FB_DIV_8(cfg->fbdiv) |
1036 inno_write(inno, 0xaa, RK3328_POST_PLL_POST_DIV_ENABLE |
1042 inno_write(inno, 0xb5 + v, phy_cfg->regs[v]);
1046 inno_update_bits(inno, 0xc8 + v, RK3328_ESD_DETECT_MASK,
1051 v = clk_get_rate(inno->sysclk) / 100000;
1052 inno_write(inno, 0xc5, RK3328_TERM_RESISTOR_CALIB_SPEED_14_8(v)
1054 inno_write(inno, 0xc6, RK3328_TERM_RESISTOR_CALIB_SPEED_7_0(v));
1055 inno_write(inno, 0xc7, RK3328_TERM_RESISTOR_100);
1056 inno_update_bits(inno, 0xc5,
1059 inno_write(inno, 0xc5, RK3328_BYPASS_TERM_RESISTOR_CALIB);
1063 inno_update_bits(inno, 0xc8,
1070 inno_update_bits(inno, 0xc9 + v,
1075 inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN, 0);
1076 inno_update_bits(inno, 0xb0, RK3328_BANDGAP_ENABLE,
1078 inno_update_bits(inno, 0xb2, RK3328_TMDS_DRIVER_ENABLE,
1082 ret = inno_poll(inno, 0xaf, v, v & RK3328_POST_PLL_LOCK_STATUS,
1085 dev_err(inno->dev, "Post-PLL locking failed\n");
1092 inno_update_bits(inno, 0x02, RK3328_PDATA_EN, RK3328_PDATA_EN);
1095 inno_write(inno, 0x05, RK3328_INT_TMDS_CLK(RK3328_INT_VSS_AGND_ESD_DET)
1097 inno_write(inno, 0x07, RK3328_INT_TMDS_D1(RK3328_INT_VSS_AGND_ESD_DET)
1102 static void inno_hdmi_phy_rk3328_power_off(struct inno_hdmi_phy *inno)
1104 inno_update_bits(inno, 0xb2, RK3328_TMDS_DRIVER_ENABLE, 0);
1105 inno_update_bits(inno, 0xb0, RK3328_BANDGAP_ENABLE, 0);
1106 inno_update_bits(inno, 0xaa, RK3328_POST_PLL_POWER_DOWN,
1110 inno_write(inno, 0x05, 0);
1111 inno_write(inno, 0x07, 0);
1141 struct inno_hdmi_phy *inno = data;
1143 clk_disable_unprepare(inno->refpclk);
1144 clk_disable_unprepare(inno->sysclk);
1149 struct inno_hdmi_phy *inno;
1155 inno = devm_kzalloc(&pdev->dev, sizeof(*inno), GFP_KERNEL);
1156 if (!inno)
1159 inno->dev = &pdev->dev;
1161 inno->plat_data = of_device_get_match_data(inno->dev);
1162 if (!inno->plat_data || !inno->plat_data->ops)
1166 regs = devm_ioremap_resource(inno->dev, res);
1170 inno->sysclk = devm_clk_get(inno->dev, "sysclk");
1171 if (IS_ERR(inno->sysclk)) {
1172 ret = PTR_ERR(inno->sysclk);
1173 dev_err(inno->dev, "failed to get sysclk: %d\n", ret);
1177 inno->refpclk = devm_clk_get(inno->dev, "refpclk");
1178 if (IS_ERR(inno->refpclk)) {
1179 ret = PTR_ERR(inno->refpclk);
1180 dev_err(inno->dev, "failed to get ref clock: %d\n", ret);
1184 inno->refoclk = devm_clk_get(inno->dev, "refoclk");
1185 if (IS_ERR(inno->refoclk)) {
1186 ret = PTR_ERR(inno->refoclk);
1187 dev_err(inno->dev, "failed to get oscillator-ref clock: %d\n",
1192 ret = clk_prepare_enable(inno->sysclk);
1194 dev_err(inno->dev, "Cannot enable inno phy sysclk: %d\n", ret);
1202 ret = clk_prepare_enable(inno->refpclk);
1204 dev_err(inno->dev, "failed to enable refpclk\n");
1205 clk_disable_unprepare(inno->sysclk);
1209 ret = devm_add_action_or_reset(inno->dev, inno_hdmi_phy_action,
1210 inno);
1214 inno->regmap = devm_regmap_init_mmio(inno->dev, regs,
1216 if (IS_ERR(inno->regmap))
1217 return PTR_ERR(inno->regmap);
1220 inno->irq = platform_get_irq(pdev, 0);
1221 if (inno->irq > 0) {
1222 ret = devm_request_threaded_irq(inno->dev, inno->irq,
1226 dev_name(inno->dev), inno);
1231 inno->phy = devm_phy_create(inno->dev, NULL, &inno_hdmi_phy_ops);
1232 if (IS_ERR(inno->phy)) {
1233 dev_err(inno->dev, "failed to create HDMI PHY\n");
1234 return PTR_ERR(inno->phy);
1237 phy_set_drvdata(inno->phy, inno);
1238 phy_set_bus_width(inno->phy, 8);
1240 if (inno->plat_data->ops->init) {
1241 ret = inno->plat_data->ops->init(inno);
1246 ret = inno_hdmi_phy_clk_register(inno);
1250 phy_provider = devm_of_phy_provider_register(inno->dev,
1277 .name = "inno-hdmi-phy",