Lines Matching refs:inno
207 static void phy_update_bits(struct inno_dsidphy *inno,
213 orig = readl(inno->phy_base + reg);
216 writel(tmp, inno->phy_base + reg);
219 static unsigned long inno_dsidphy_pll_calc_rate(struct inno_dsidphy *inno,
222 unsigned long prate = clk_get_rate(inno->ref_clk);
281 inno->pll.prediv = best_prediv;
282 inno->pll.fbdiv = best_fbdiv;
283 inno->pll.rate = best_freq;
289 static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno)
291 struct phy_configure_opts_mipi_dphy *cfg = &inno->dphy_cfg;
317 inno_dsidphy_pll_calc_rate(inno, cfg->hs_clk_rate);
320 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
323 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
324 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
325 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
326 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv));
327 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
328 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
330 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
334 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
337 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
340 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
343 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
346 txbyteclkhs = inno->pll.rate / 8;
397 if (inno->pll.rate <= timings[i].rate)
415 phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK,
417 phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,
419 phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_MASK,
421 phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,
423 phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_MASK,
425 phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_MASK,
427 phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,
429 phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,
431 phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK,
433 phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK,
435 phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK,
437 phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK,
442 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
447 static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno)
453 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
458 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
461 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
463 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
465 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
467 phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc);
469 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
476 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
480 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
484 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
488 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
496 struct inno_dsidphy *inno = phy_get_drvdata(phy);
498 clk_prepare_enable(inno->pclk_phy);
499 clk_prepare_enable(inno->ref_clk);
500 pm_runtime_get_sync(inno->dev);
503 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
506 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
509 switch (inno->mode) {
511 inno_dsidphy_mipi_mode_enable(inno);
514 inno_dsidphy_lvds_mode_enable(inno);
525 struct inno_dsidphy *inno = phy_get_drvdata(phy);
527 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0);
528 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
531 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
533 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
536 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0);
537 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
540 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
544 pm_runtime_put(inno->dev);
545 clk_disable_unprepare(inno->ref_clk);
546 clk_disable_unprepare(inno->pclk_phy);
554 struct inno_dsidphy *inno = phy_get_drvdata(phy);
559 inno->mode = mode;
571 struct inno_dsidphy *inno = phy_get_drvdata(phy);
574 if (inno->mode != PHY_MODE_MIPI_DPHY)
581 memcpy(&inno->dphy_cfg, &opts->mipi_dphy, sizeof(inno->dphy_cfg));
597 struct inno_dsidphy *inno;
602 inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
603 if (!inno)
606 inno->dev = dev;
607 platform_set_drvdata(pdev, inno);
609 inno->phy_base = devm_platform_ioremap_resource(pdev, 0);
610 if (IS_ERR(inno->phy_base))
611 return PTR_ERR(inno->phy_base);
613 inno->ref_clk = devm_clk_get(dev, "ref");
614 if (IS_ERR(inno->ref_clk)) {
615 ret = PTR_ERR(inno->ref_clk);
620 inno->pclk_phy = devm_clk_get(dev, "pclk");
621 if (IS_ERR(inno->pclk_phy)) {
622 ret = PTR_ERR(inno->pclk_phy);
627 inno->rst = devm_reset_control_get(dev, "apb");
628 if (IS_ERR(inno->rst)) {
629 ret = PTR_ERR(inno->rst);
641 phy_set_drvdata(phy, inno);
657 struct inno_dsidphy *inno = platform_get_drvdata(pdev);
659 pm_runtime_disable(inno->dev);
674 .name = "inno-dsidphy",