Lines Matching defs:phy_update_bits
207 static void phy_update_bits(struct inno_dsidphy *inno,
320 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
323 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
325 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
327 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
330 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
334 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
337 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
340 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
343 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
415 phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK,
417 phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,
419 phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_MASK,
421 phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,
423 phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_MASK,
425 phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_MASK,
427 phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,
429 phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,
431 phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK,
433 phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK,
435 phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK,
437 phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK,
442 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
453 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
458 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
461 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
463 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
465 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
467 phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc);
469 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
476 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
480 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
484 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
488 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
503 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
506 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
527 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0);
528 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
531 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
533 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
536 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0);
537 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
540 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,