Lines Matching refs:qphy_setbits
1972 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
2667 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
2957 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
2960 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2965 qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
2967 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
2980 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
2984 qphy_setbits(pcs,
2988 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
3022 qphy_setbits(serdes, cfg->regs[QPHY_COM_START_CONTROL],
3026 qphy_setbits(serdes, cfg->regs[QPHY_COM_POWER_DOWN_CONTROL],
3154 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
3164 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
3207 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
3287 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
3295 qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
3310 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
3315 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);