Lines Matching defs:qphy
1936 struct qmp_phy *qphy;
2621 static int qcom_qmp_phy_serdes_init(struct qmp_phy *qphy)
2623 struct qcom_qmp *qmp = qphy->qmp;
2624 const struct qmp_phy_cfg *cfg = qphy->cfg;
2625 void __iomem *serdes = qphy->serdes;
2626 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
2685 static void qcom_qmp_phy_dp_aux_init(struct qmp_phy *qphy)
2689 qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
2694 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
2696 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
2702 qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
2708 qphy->serdes + QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN);
2710 writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG0);
2711 writel(0x13, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);
2712 writel(0x24, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
2713 writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG3);
2714 writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG4);
2715 writel(0x26, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG5);
2716 writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG6);
2717 writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG7);
2718 writel(0xbb, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG8);
2719 writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG9);
2720 qphy->dp_aux_cfg = 0;
2725 qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
2742 static void qcom_qmp_phy_configure_dp_tx(struct qmp_phy *qphy)
2744 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
2774 writel(voltage_swing_cfg, qphy->tx + QSERDES_V3_TX_TX_DRV_LVL);
2775 writel(pre_emphasis_cfg, qphy->tx + QSERDES_V3_TX_TX_EMP_POST1_LVL);
2776 writel(voltage_swing_cfg, qphy->tx2 + QSERDES_V3_TX_TX_DRV_LVL);
2777 writel(pre_emphasis_cfg, qphy->tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL);
2779 writel(drvr_en, qphy->tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
2780 writel(bias_en, qphy->tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
2781 writel(drvr_en, qphy->tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
2782 writel(bias_en, qphy->tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
2788 struct qmp_phy *qphy = phy_get_drvdata(phy);
2790 memcpy(&qphy->dp_opts, dp_opts, sizeof(*dp_opts));
2791 if (qphy->dp_opts.set_voltages) {
2792 qcom_qmp_phy_configure_dp_tx(qphy);
2793 qphy->dp_opts.set_voltages = 0;
2799 static int qcom_qmp_phy_configure_dp_phy(struct qmp_phy *qphy)
2801 const struct qmp_phy_dp_clks *dp_clks = qphy->dp_clks;
2802 const struct phy_configure_opts_dp *dp_opts = &qphy->dp_opts;
2821 * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
2824 writel(val, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
2826 writel(0x5c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
2827 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
2828 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
2851 writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
2856 writel(0x04, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
2857 writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
2858 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
2859 writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
2860 writel(0x09, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
2862 writel(0x20, qphy->serdes + QSERDES_V3_COM_RESETSM_CNTRL);
2864 if (readl_poll_timeout(qphy->serdes + QSERDES_V3_COM_C_READY_STATUS,
2871 writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
2873 if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
2880 writel(0x18, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
2882 writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
2884 return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
2897 struct qmp_phy *qphy = phy_get_drvdata(phy);
2901 qphy->dp_aux_cfg++;
2902 qphy->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
2903 val = cfg1_settings[qphy->dp_aux_cfg];
2905 writel(val, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);
2910 static int qcom_qmp_phy_com_init(struct qmp_phy *qphy)
2912 struct qcom_qmp *qmp = qphy->qmp;
2913 const struct qmp_phy_cfg *cfg = qphy->cfg;
2914 void __iomem *serdes = qphy->serdes;
2915 void __iomem *pcs = qphy->pcs;
2945 qphy->cfg->reset_list[i]);
3007 static int qcom_qmp_phy_com_exit(struct qmp_phy *qphy)
3009 struct qcom_qmp *qmp = qphy->qmp;
3010 const struct qmp_phy_cfg *cfg = qphy->cfg;
3011 void __iomem *serdes = qphy->serdes;
3044 struct qmp_phy *qphy = phy_get_drvdata(phy);
3045 struct qcom_qmp *qmp = qphy->qmp;
3046 const struct qmp_phy_cfg *cfg = qphy->cfg;
3077 ret = qcom_qmp_phy_com_init(qphy);
3082 qcom_qmp_phy_dp_aux_init(qphy);
3089 struct qmp_phy *qphy = phy_get_drvdata(phy);
3090 struct qcom_qmp *qmp = qphy->qmp;
3091 const struct qmp_phy_cfg *cfg = qphy->cfg;
3092 void __iomem *tx = qphy->tx;
3093 void __iomem *rx = qphy->rx;
3094 void __iomem *pcs = qphy->pcs;
3095 void __iomem *pcs_misc = qphy->pcs_misc;
3100 qcom_qmp_phy_serdes_init(qphy);
3103 ret = reset_control_deassert(qphy->lane_rst);
3106 qphy->index);
3111 ret = clk_prepare_enable(qphy->pipe_clk);
3122 qcom_qmp_phy_configure_lane(qphy->tx2, cfg->regs,
3127 qcom_qmp_phy_configure_dp_tx(qphy);
3133 qcom_qmp_phy_configure_lane(qphy->rx2, cfg->regs,
3138 qcom_qmp_phy_configure_dp_phy(qphy);
3186 clk_disable_unprepare(qphy->pipe_clk);
3189 reset_control_assert(qphy->lane_rst);
3196 struct qmp_phy *qphy = phy_get_drvdata(phy);
3197 const struct qmp_phy_cfg *cfg = qphy->cfg;
3199 clk_disable_unprepare(qphy->pipe_clk);
3203 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
3207 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
3210 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
3214 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
3217 qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
3227 struct qmp_phy *qphy = phy_get_drvdata(phy);
3228 const struct qmp_phy_cfg *cfg = qphy->cfg;
3231 reset_control_assert(qphy->lane_rst);
3233 qcom_qmp_phy_com_exit(qphy);
3266 struct qmp_phy *qphy = phy_get_drvdata(phy);
3268 qphy->mode = mode;
3273 static void qcom_qmp_phy_enable_autonomous_mode(struct qmp_phy *qphy)
3275 const struct qmp_phy_cfg *cfg = qphy->cfg;
3276 void __iomem *pcs = qphy->pcs;
3277 void __iomem *pcs_misc = qphy->pcs_misc;
3280 if (qphy->mode == PHY_MODE_USB_HOST_SS ||
3281 qphy->mode == PHY_MODE_USB_DEVICE_SS)
3302 static void qcom_qmp_phy_disable_autonomous_mode(struct qmp_phy *qphy)
3304 const struct qmp_phy_cfg *cfg = qphy->cfg;
3305 void __iomem *pcs = qphy->pcs;
3306 void __iomem *pcs_misc = qphy->pcs_misc;
3323 struct qmp_phy *qphy = qmp->phys[0];
3324 const struct qmp_phy_cfg *cfg = qphy->cfg;
3326 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
3337 qcom_qmp_phy_enable_autonomous_mode(qphy);
3339 clk_disable_unprepare(qphy->pipe_clk);
3348 struct qmp_phy *qphy = qmp->phys[0];
3349 const struct qmp_phy_cfg *cfg = qphy->cfg;
3352 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
3369 ret = clk_prepare_enable(qphy->pipe_clk);
3376 qcom_qmp_phy_disable_autonomous_mode(qphy);
3568 const struct qmp_phy *qphy;
3572 qphy = dp_clks->qphy;
3573 dp_opts = &qphy->dp_opts;
3612 const struct qmp_phy *qphy;
3616 qphy = dp_clks->qphy;
3617 dp_opts = &qphy->dp_opts;
3652 static int phy_dp_clks_register(struct qcom_qmp *qmp, struct qmp_phy *qphy,
3663 dp_clks->qphy = qphy;
3664 qphy->dp_clks = dp_clks;
3731 struct qmp_phy *qphy;
3736 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
3737 if (!qphy)
3740 qphy->cfg = cfg;
3741 qphy->serdes = serdes;
3748 qphy->tx = of_iomap(np, 0);
3749 if (!qphy->tx)
3752 qphy->rx = of_iomap(np, 1);
3753 if (!qphy->rx)
3756 qphy->pcs = of_iomap(np, 2);
3757 if (!qphy->pcs)
3767 qphy->tx2 = of_iomap(np, 3);
3768 qphy->rx2 = of_iomap(np, 4);
3769 if (!qphy->tx2 || !qphy->rx2) {
3774 qphy->pcs_misc = qphy->tx2;
3775 qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
3776 qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
3779 qphy->pcs_misc = of_iomap(np, 5);
3783 qphy->pcs_misc = of_iomap(np, 3);
3786 if (!qphy->pcs_misc)
3797 qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
3798 if (IS_ERR(qphy->pipe_clk)) {
3801 ret = PTR_ERR(qphy->pipe_clk);
3808 qphy->pipe_clk = NULL;
3814 qphy->lane_rst = of_reset_control_get(np, prop_name);
3815 if (IS_ERR(qphy->lane_rst)) {
3817 return PTR_ERR(qphy->lane_rst);
3820 qphy->lane_rst);
3835 dev_err(dev, "failed to create qphy %d\n", ret);
3839 qphy->phy = generic_phy;
3840 qphy->index = id;
3841 qphy->qmp = qmp;
3842 qmp->phys[id] = qphy;
3843 phy_set_drvdata(generic_phy, qphy);