Lines Matching defs:pcs
1834 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1905 * @pcs: iomapped memory space for lane's pcs
1921 void __iomem *pcs;
2689 qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
2696 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
2702 qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
2710 writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG0);
2711 writel(0x13, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);
2712 writel(0x24, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
2713 writel(0x00, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG3);
2714 writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG4);
2715 writel(0x26, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG5);
2716 writel(0x0a, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG6);
2717 writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG7);
2718 writel(0xbb, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG8);
2719 writel(0x03, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG9);
2725 qphy->pcs + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
2821 * writel(0x4c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
2824 writel(val, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
2826 writel(0x5c, qphy->pcs + QSERDES_V3_DP_PHY_MODE);
2827 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
2828 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
2851 writel(phy_vco_div, qphy->pcs + QSERDES_V3_DP_PHY_VCO_DIV);
2856 writel(0x04, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG2);
2857 writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
2858 writel(0x05, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
2859 writel(0x01, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
2860 writel(0x09, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
2871 writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
2873 if (readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
2880 writel(0x18, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
2882 writel(0x19, qphy->pcs + QSERDES_V3_DP_PHY_CFG);
2884 return readl_poll_timeout(qphy->pcs + QSERDES_V3_DP_PHY_STATUS,
2905 writel(val, qphy->pcs + QSERDES_V3_DP_PHY_AUX_CFG1);
2915 void __iomem *pcs = qphy->pcs;
2984 qphy_setbits(pcs,
2988 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL,
3094 void __iomem *pcs = qphy->pcs;
3140 qcom_qmp_phy_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
3154 qphy_setbits(pcs, QPHY_POWER_DOWN_CONTROL, cfg->pwrdn_ctrl);
3162 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
3164 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
3167 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
3171 status = pcs + cfg->regs[QPHY_PCS_STATUS];
3203 writel(DP_PHY_PD_CTL_PSR_PWRDN, qphy->pcs + QSERDES_V3_DP_PHY_PD_CTL);
3207 qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
3210 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
3214 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
3217 qphy_clrbits(qphy->pcs, QPHY_POWER_DOWN_CONTROL,
3276 void __iomem *pcs = qphy->pcs;
3287 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
3289 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
3291 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
3295 qphy_setbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
3305 void __iomem *pcs = qphy->pcs;
3312 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
3315 qphy_setbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
3317 qphy_clrbits(pcs, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
3744 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
3756 qphy->pcs = of_iomap(np, 2);
3757 if (!qphy->pcs)