Lines Matching defs:qphy
52 struct qcom_phy *qphy = phy_get_drvdata(phy);
55 ret = reset_control_deassert(qphy->phy_reset);
57 dev_err(qphy->dev, "cannot deassert pipe reset\n");
61 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
63 reset_control_assert(qphy->phy_reset);
70 struct qcom_phy *qphy = phy_get_drvdata(phy);
75 val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
77 writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
82 val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
84 writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL2);
87 val = readl(qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3);
89 writel(val, qphy->base + PCIE20_PARF_PHY_REFCLK_CTRL3);
94 val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
96 writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
99 val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL1);
102 writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL1);
104 val = readl(qphy->base + PCIE20_PARF_PCS_SWING_CTRL2);
107 writel(val, qphy->base + PCIE20_PARF_PCS_SWING_CTRL2);
110 val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH1);
113 writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH1);
115 val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH2);
118 writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH2);
120 val = readl(qphy->base + PCIE20_PARF_PCS_DEEMPH3);
123 writel(val, qphy->base + PCIE20_PARF_PCS_DEEMPH3);
126 val = readl(qphy->base + PCIE20_PARF_CONFIGBITS);
129 writel(val, qphy->base + PCIE20_PARF_CONFIGBITS);
132 val = readl(qphy->base + PCIE20_PARF_PHY_CTRL3);
135 writel(val, qphy->base + PCIE20_PARF_PHY_CTRL3);
138 val = readl(qphy->base + PCIE20_PARF_PCS_CTRL);
140 writel(val, qphy->base + PCIE20_PARF_PCS_CTRL);
143 val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
145 writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
149 ret = reset_control_deassert(qphy->pipe_reset);
151 dev_err(qphy->dev, "cannot deassert pipe reset\n");
155 clk_set_rate(qphy->pipe_clk, 250000000);
157 ret = clk_prepare_enable(qphy->pipe_clk);
159 dev_err(qphy->dev, "failed to enable pipe clock\n");
163 ret = readl_poll_timeout(qphy->base + PCIE20_PARF_PHY_STTS, val,
166 dev_err(qphy->dev, "phy initialization failed\n");
174 struct qcom_phy *qphy = phy_get_drvdata(phy);
177 val = readl(qphy->base + PCIE2_PHY_RESET_CTRL);
179 writel(val, qphy->base + PCIE2_PHY_RESET_CTRL);
181 clk_disable_unprepare(qphy->pipe_clk);
182 reset_control_assert(qphy->pipe_reset);
189 struct qcom_phy *qphy = phy_get_drvdata(phy);
191 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs);
192 reset_control_assert(qphy->phy_reset);
223 static int phy_pipe_clksrc_register(struct qcom_phy *qphy)
225 struct device_node *np = qphy->dev->of_node;
232 dev_err(qphy->dev, "%s: No clock-output-names\n", np->name);
236 fixed = devm_kzalloc(qphy->dev, sizeof(*fixed), GFP_KERNEL);
246 return devm_clk_hw_register(qphy->dev, &fixed->hw);
252 struct qcom_phy *qphy;
258 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
259 if (!qphy)
262 qphy->dev = dev;
265 qphy->base = devm_ioremap_resource(dev, res);
266 if (IS_ERR(qphy->base))
267 return PTR_ERR(qphy->base);
269 ret = phy_pipe_clksrc_register(qphy);
275 qphy->vregs[0].supply = "vdda-vp";
276 qphy->vregs[1].supply = "vdda-vph";
277 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(qphy->vregs), qphy->vregs);
281 qphy->pipe_clk = devm_clk_get(dev, NULL);
282 if (IS_ERR(qphy->pipe_clk)) {
284 return PTR_ERR(qphy->pipe_clk);
287 qphy->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
288 if (IS_ERR(qphy->phy_reset)) {
290 return PTR_ERR(qphy->phy_reset);
293 qphy->pipe_reset = devm_reset_control_get_exclusive(dev, "pipe");
294 if (IS_ERR(qphy->pipe_reset)) {
296 return PTR_ERR(qphy->pipe_reset);
305 phy_set_drvdata(phy, qphy);