Lines Matching refs:phy_dwc3
137 static inline void usb_phy_write_readback(struct usb_phy *phy_dwc3,
141 u32 write_val, tmp = readl(phy_dwc3->base + offset);
146 writel(write_val, phy_dwc3->base + offset);
149 tmp = readl(phy_dwc3->base + offset);
153 dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n", val, offset);
180 static int usb_ss_write_phycreg(struct usb_phy *phy_dwc3,
185 writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
187 phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
189 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
193 writel(val, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
195 phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
197 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
201 writel(SS_CR_WRITE_REG, phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
203 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
207 dev_err(phy_dwc3->dev, "timeout waiting for latch\n");
217 static int usb_ss_read_phycreg(struct usb_phy *phy_dwc3,
222 writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
224 phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
226 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
235 writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
237 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
242 readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
244 writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
246 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
250 *val = readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
258 struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
262 ret = clk_prepare_enable(phy_dwc3->xo_clk);
266 ret = clk_prepare_enable(phy_dwc3->ref_clk);
268 clk_disable_unprepare(phy_dwc3->xo_clk);
283 if (!phy_dwc3->xo_clk)
286 writel(val, phy_dwc3->base + HSUSB_PHY_CTRL_REG);
290 writel(HSUSB_GCFG_XHCI_REV, phy_dwc3->base + QSCRATCH_GENERAL_CFG);
297 struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
299 clk_disable_unprepare(phy_dwc3->ref_clk);
300 clk_disable_unprepare(phy_dwc3->xo_clk);
307 struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
311 ret = clk_prepare_enable(phy_dwc3->xo_clk);
315 ret = clk_prepare_enable(phy_dwc3->ref_clk);
317 clk_disable_unprepare(phy_dwc3->xo_clk);
322 data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG);
324 phy_dwc3->base + SSUSB_PHY_CTRL_REG);
326 writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
329 if (!phy_dwc3->xo_clk)
334 writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
340 writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
347 ret = usb_ss_read_phycreg(phy_dwc3, 0x102D, &data);
352 ret = usb_ss_write_phycreg(phy_dwc3, 0x102D, data);
356 ret = usb_ss_read_phycreg(phy_dwc3, 0x1010, &data);
362 ret = usb_ss_write_phycreg(phy_dwc3, 0x1010, data);
373 ret = usb_ss_read_phycreg(phy_dwc3, SSPHY_CTRL_RX_OVRD_IN_HI(0), &data);
380 data |= RX_OVRD_IN_HI_RX_EQ(phy_dwc3->rx_eq);
382 ret = usb_ss_write_phycreg(phy_dwc3,
393 ret = usb_ss_read_phycreg(phy_dwc3,
399 data |= TX_OVRD_DRV_LO_PREEMPH(phy_dwc3->tx_deamp_3_5db);
403 ret = usb_ss_write_phycreg(phy_dwc3,
410 data |= SSPHY_MPLL(phy_dwc3->mpll);
411 usb_ss_write_phycreg(phy_dwc3, 0x30, data);
420 data = readl(phy_dwc3->base + SSUSB_PHY_PARAM_CTRL_1);
426 PHY_PARAM_CTRL1_TX_DEEMPH_3_5DB(phy_dwc3->tx_deamp_3_5db) |
429 usb_phy_write_readback(phy_dwc3, SSUSB_PHY_PARAM_CTRL_1,
438 struct usb_phy *phy_dwc3 = phy_get_drvdata(phy);
445 usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
447 usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
449 usb_phy_write_readback(phy_dwc3, SSUSB_PHY_CTRL_REG,
452 clk_disable_unprepare(phy_dwc3->ref_clk);
453 clk_disable_unprepare(phy_dwc3->xo_clk);
490 struct usb_phy *phy_dwc3;
494 phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL);
495 if (!phy_dwc3)
500 phy_dwc3->dev = &pdev->dev;
506 phy_dwc3->base = devm_ioremap(phy_dwc3->dev, res->start, size);
508 if (!phy_dwc3->base) {
509 dev_err(phy_dwc3->dev, "failed to map reg\n");
513 phy_dwc3->ref_clk = devm_clk_get(phy_dwc3->dev, "ref");
514 if (IS_ERR(phy_dwc3->ref_clk)) {
515 dev_dbg(phy_dwc3->dev, "cannot get reference clock\n");
516 return PTR_ERR(phy_dwc3->ref_clk);
519 clk_set_rate(phy_dwc3->ref_clk, data->clk_rate);
521 phy_dwc3->xo_clk = devm_clk_get(phy_dwc3->dev, "xo");
522 if (IS_ERR(phy_dwc3->xo_clk)) {
523 dev_dbg(phy_dwc3->dev, "cannot get TCXO clock\n");
524 phy_dwc3->xo_clk = NULL;
529 &phy_dwc3->rx_eq))
530 phy_dwc3->rx_eq = SSPHY_RX_EQ_VALUE;
533 &phy_dwc3->tx_deamp_3_5db))
534 phy_dwc3->tx_deamp_3_5db = SSPHY_TX_DEEMPH_3_5DB;
536 if (device_property_read_u32(&pdev->dev, "qcom,mpll", &phy_dwc3->mpll))
537 phy_dwc3->mpll = SSPHY_MPLL_VALUE;
539 generic_phy = devm_phy_create(phy_dwc3->dev, pdev->dev.of_node, &data->ops);
544 phy_set_drvdata(generic_phy, phy_dwc3);
545 platform_set_drvdata(pdev, phy_dwc3);
547 phy_provider = devm_of_phy_provider_register(phy_dwc3->dev,