Lines Matching refs:base
115 void __iomem *base;
132 * @base - QCOM DWC3 PHY base virtual address.
141 u32 write_val, tmp = readl(phy_dwc3->base + offset);
146 writel(write_val, phy_dwc3->base + offset);
149 tmp = readl(phy_dwc3->base + offset);
176 * @base - QCOM DWC3 PHY base virtual address.
185 writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
187 phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
189 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
193 writel(val, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
195 phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
197 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_DATA_REG);
201 writel(SS_CR_WRITE_REG, phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
203 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_WRITE_REG);
214 * @base - QCOM DWC3 PHY base virtual address.
222 writel(addr, phy_dwc3->base + CR_PROTOCOL_DATA_IN_REG);
224 phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
226 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_CAP_ADDR_REG);
235 writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
237 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
242 readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
244 writel(SS_CR_READ_REG, phy_dwc3->base + CR_PROTOCOL_READ_REG);
246 ret = wait_for_latch(phy_dwc3->base + CR_PROTOCOL_READ_REG);
250 *val = readl(phy_dwc3->base + CR_PROTOCOL_DATA_OUT_REG);
286 writel(val, phy_dwc3->base + HSUSB_PHY_CTRL_REG);
290 writel(HSUSB_GCFG_XHCI_REV, phy_dwc3->base + QSCRATCH_GENERAL_CFG);
322 data = readl(phy_dwc3->base + SSUSB_PHY_CTRL_REG);
324 phy_dwc3->base + SSUSB_PHY_CTRL_REG);
326 writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
334 writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
340 writel(data, phy_dwc3->base + SSUSB_PHY_CTRL_REG);
420 data = readl(phy_dwc3->base + SSUSB_PHY_PARAM_CTRL_1);
506 phy_dwc3->base = devm_ioremap(phy_dwc3->dev, res->start, size);
508 if (!phy_dwc3->base) {