Lines Matching refs:p_phy
54 struct pistachio_usb_phy *p_phy = phy_get_drvdata(phy);
59 ret = clk_prepare_enable(p_phy->phy_clk);
61 dev_err(p_phy->dev, "Failed to enable PHY clock: %d\n", ret);
65 regmap_update_bits(p_phy->cr_top, USB_PHY_STRAP_CONTROL,
68 p_phy->refclk << USB_PHY_STRAP_CONTROL_REFCLK_SHIFT);
70 rate = clk_get_rate(p_phy->phy_clk);
71 if (p_phy->refclk == REFCLK_XO_CRYSTAL && rate != 12000000) {
72 dev_err(p_phy->dev, "Unsupported rate for XO crystal: %ld\n",
83 dev_err(p_phy->dev, "Unsupported clock rate: %lu\n", rate);
88 regmap_update_bits(p_phy->cr_top, USB_PHY_CONTROL1,
97 regmap_read(p_phy->cr_top, USB_PHY_STATUS, &val);
99 dev_err(p_phy->dev, "VBUS fault detected\n");
109 dev_err(p_phy->dev, "Timed out waiting for PHY to power on\n");
113 clk_disable_unprepare(p_phy->phy_clk);
119 struct pistachio_usb_phy *p_phy = phy_get_drvdata(phy);
121 clk_disable_unprepare(p_phy->phy_clk);
134 struct pistachio_usb_phy *p_phy;
139 p_phy = devm_kzalloc(&pdev->dev, sizeof(*p_phy), GFP_KERNEL);
140 if (!p_phy)
142 p_phy->dev = &pdev->dev;
143 platform_set_drvdata(pdev, p_phy);
145 p_phy->cr_top = syscon_regmap_lookup_by_phandle(p_phy->dev->of_node,
147 if (IS_ERR(p_phy->cr_top)) {
148 dev_err(p_phy->dev, "Failed to get CR_TOP registers: %ld\n",
149 PTR_ERR(p_phy->cr_top));
150 return PTR_ERR(p_phy->cr_top);
153 p_phy->phy_clk = devm_clk_get(p_phy->dev, "usb_phy");
154 if (IS_ERR(p_phy->phy_clk)) {
155 dev_err(p_phy->dev, "Failed to get usb_phy clock: %ld\n",
156 PTR_ERR(p_phy->phy_clk));
157 return PTR_ERR(p_phy->phy_clk);
160 ret = of_property_read_u32(p_phy->dev->of_node, "img,refclk",
161 &p_phy->refclk);
163 dev_err(p_phy->dev, "No reference clock selector specified\n");
167 phy = devm_phy_create(p_phy->dev, NULL, &pistachio_usb_phy_ops);
169 dev_err(p_phy->dev, "Failed to create PHY: %ld\n",
173 phy_set_drvdata(phy, p_phy);
175 provider = devm_of_phy_provider_register(p_phy->dev,
178 dev_err(p_phy->dev, "Failed to register PHY provider: %ld\n",