Lines Matching refs:phy
11 #include <linux/phy/phy.h>
41 static inline u32 mphy_readl(struct ufs_mtk_phy *phy, u32 reg)
43 return readl(phy->mmio + reg);
46 static inline void mphy_writel(struct ufs_mtk_phy *phy, u32 val, u32 reg)
48 writel(val, phy->mmio + reg);
51 static void mphy_set_bit(struct ufs_mtk_phy *phy, u32 reg, u32 bit)
55 val = mphy_readl(phy, reg);
57 mphy_writel(phy, val, reg);
60 static void mphy_clr_bit(struct ufs_mtk_phy *phy, u32 reg, u32 bit)
64 val = mphy_readl(phy, reg);
66 mphy_writel(phy, val, reg);
69 static struct ufs_mtk_phy *get_ufs_mtk_phy(struct phy *generic_phy)
74 static int ufs_mtk_phy_clk_init(struct ufs_mtk_phy *phy)
76 struct device *dev = phy->dev;
78 phy->unipro_clk = devm_clk_get(dev, "unipro");
79 if (IS_ERR(phy->unipro_clk)) {
81 return PTR_ERR(phy->unipro_clk);
84 phy->mp_clk = devm_clk_get(dev, "mp");
85 if (IS_ERR(phy->mp_clk)) {
87 return PTR_ERR(phy->mp_clk);
93 static void ufs_mtk_phy_set_active(struct ufs_mtk_phy *phy)
96 mphy_set_bit(phy, MP_GLB_DIG_8C, PLL_PWR_ON);
97 mphy_clr_bit(phy, MP_GLB_DIG_8C, FRC_FRC_PWR_ON);
100 mphy_clr_bit(phy, MP_GLB_DIG_8C, PLL_ISO_EN);
101 mphy_clr_bit(phy, MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
104 mphy_set_bit(phy, MP_LN_RX_44, CDR_PWR_ON);
105 mphy_clr_bit(phy, MP_LN_RX_44, FRC_CDR_PWR_ON);
108 mphy_clr_bit(phy, MP_LN_RX_44, CDR_ISO_EN);
109 mphy_clr_bit(phy, MP_LN_RX_44, FRC_CDR_ISO_EN);
112 mphy_set_bit(phy, MP_LN_DIG_RX_AC, RX_SQ_EN);
113 mphy_clr_bit(phy, MP_LN_DIG_RX_AC, FRC_RX_SQ_EN);
119 mphy_clr_bit(phy, MP_LN_DIG_RX_9C, FSM_DIFZ_FRC);
122 static void ufs_mtk_phy_set_deep_hibern(struct ufs_mtk_phy *phy)
125 mphy_set_bit(phy, MP_LN_DIG_RX_9C, FSM_DIFZ_FRC);
128 mphy_set_bit(phy, MP_LN_DIG_RX_AC, FRC_RX_SQ_EN);
129 mphy_clr_bit(phy, MP_LN_DIG_RX_AC, RX_SQ_EN);
132 mphy_set_bit(phy, MP_LN_RX_44, FRC_CDR_ISO_EN);
133 mphy_set_bit(phy, MP_LN_RX_44, CDR_ISO_EN);
136 mphy_set_bit(phy, MP_LN_RX_44, FRC_CDR_PWR_ON);
137 mphy_clr_bit(phy, MP_LN_RX_44, CDR_PWR_ON);
140 mphy_set_bit(phy, MP_GLB_DIG_8C, FRC_PLL_ISO_EN);
141 mphy_set_bit(phy, MP_GLB_DIG_8C, PLL_ISO_EN);
144 mphy_set_bit(phy, MP_GLB_DIG_8C, FRC_FRC_PWR_ON);
145 mphy_clr_bit(phy, MP_GLB_DIG_8C, PLL_PWR_ON);
148 static int ufs_mtk_phy_power_on(struct phy *generic_phy)
150 struct ufs_mtk_phy *phy = get_ufs_mtk_phy(generic_phy);
153 ret = clk_prepare_enable(phy->unipro_clk);
155 dev_err(phy->dev, "unipro_clk enable failed %d\n", ret);
159 ret = clk_prepare_enable(phy->mp_clk);
161 dev_err(phy->dev, "mp_clk enable failed %d\n", ret);
165 ufs_mtk_phy_set_active(phy);
170 clk_disable_unprepare(phy->unipro_clk);
175 static int ufs_mtk_phy_power_off(struct phy *generic_phy)
177 struct ufs_mtk_phy *phy = get_ufs_mtk_phy(generic_phy);
179 ufs_mtk_phy_set_deep_hibern(phy);
181 clk_disable_unprepare(phy->unipro_clk);
182 clk_disable_unprepare(phy->mp_clk);
196 struct phy *generic_phy;
199 struct ufs_mtk_phy *phy;
202 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
203 if (!phy)
207 phy->mmio = devm_ioremap_resource(dev, res);
208 if (IS_ERR(phy->mmio))
209 return PTR_ERR(phy->mmio);
211 phy->dev = dev;
213 ret = ufs_mtk_phy_clk_init(phy);
221 phy_set_drvdata(generic_phy, phy);