Lines Matching refs:tmp
331 u32 tmp;
338 tmp = readl(com + U3P_USBPHYACR5);
339 tmp |= PA5_RG_U2_HSTX_SRCAL_EN;
340 writel(tmp, com + U3P_USBPHYACR5);
344 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1);
345 tmp |= P2F_RG_FRCK_EN;
346 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1);
349 tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
350 tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL);
351 tmp |= P2F_RG_CYCLECNT_VAL(U3P_FM_DET_CYCLE_CNT);
353 tmp |= P2F_RG_MONCLK_SEL_VAL(instance->index >> 1);
355 writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
358 tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
359 tmp |= P2F_RG_FREQDET_EN;
360 writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
363 readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp,
364 (tmp & P2F_USB_FM_VALID), 10, 200);
369 tmp = readl(fmreg + U3P_U2FREQ_FMCR0);
370 tmp &= ~P2F_RG_FREQDET_EN;
371 writel(tmp, fmreg + U3P_U2FREQ_FMCR0);
374 tmp = readl(fmreg + U3P_U2FREQ_FMMONR1);
375 tmp &= ~P2F_RG_FRCK_EN;
376 writel(tmp, fmreg + U3P_U2FREQ_FMMONR1);
380 tmp = tphy->src_ref_clk * tphy->src_coef;
381 tmp = (tmp * U3P_FM_DET_CYCLE_CNT) / fm_out;
382 calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR);
392 tmp = readl(com + U3P_USBPHYACR5);
393 tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
394 tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(calibration_val);
395 writel(tmp, com + U3P_USBPHYACR5);
398 tmp = readl(com + U3P_USBPHYACR5);
399 tmp &= ~PA5_RG_U2_HSTX_SRCAL_EN;
400 writel(tmp, com + U3P_USBPHYACR5);
407 u32 tmp;
410 tmp = readl(u3_banks->spllc + U3P_SPLLC_XTALCTL3);
411 tmp |= XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD;
412 writel(tmp, u3_banks->spllc + U3P_SPLLC_XTALCTL3);
415 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
416 tmp &= ~P3A_RG_XTAL_EXT_EN_U3;
417 tmp |= P3A_RG_XTAL_EXT_EN_U3_VAL(2);
418 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0);
420 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG9);
421 tmp &= ~P3A_RG_RX_DAC_MUX;
422 tmp |= P3A_RG_RX_DAC_MUX_VAL(4);
423 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG9);
425 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG6);
426 tmp &= ~P3A_RG_TX_EIDLE_CM;
427 tmp |= P3A_RG_TX_EIDLE_CM_VAL(0xe);
428 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG6);
430 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_CDR1);
431 tmp &= ~(P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1);
432 tmp |= P3D_RG_CDR_BIR_LTD0_VAL(0xc) | P3D_RG_CDR_BIR_LTD1_VAL(0x3);
433 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_CDR1);
435 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_LFPS1);
436 tmp &= ~P3D_RG_FWAKE_TH;
437 tmp |= P3D_RG_FWAKE_TH_VAL(0x34);
438 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_LFPS1);
440 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1);
441 tmp &= ~P3D_RG_RXDET_STB2_SET;
442 tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10);
443 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1);
445 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2);
446 tmp &= ~P3D_RG_RXDET_STB2_SET_P3;
447 tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10);
448 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2);
459 u32 tmp;
462 tmp = readl(com + U3P_U2PHYDTM0);
463 tmp &= ~(P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM);
464 tmp |= P2C_RG_XCVRSEL_VAL(1) | P2C_RG_DATAIN_VAL(0);
465 writel(tmp, com + U3P_U2PHYDTM0);
467 tmp = readl(com + U3P_U2PHYDTM1);
468 tmp &= ~P2C_RG_UART_EN;
469 writel(tmp, com + U3P_U2PHYDTM1);
471 tmp = readl(com + U3P_USBPHYACR0);
472 tmp |= PA0_RG_USB20_INTR_EN;
473 writel(tmp, com + U3P_USBPHYACR0);
476 tmp = readl(com + U3P_USBPHYACR5);
477 tmp &= ~PA5_RG_U2_HS_100U_U3_EN;
478 writel(tmp, com + U3P_USBPHYACR5);
481 tmp = readl(com + U3P_U2PHYACR4);
482 tmp &= ~P2C_U2_GPIO_CTR_MSK;
483 writel(tmp, com + U3P_U2PHYACR4);
488 tmp = readl(com + U3P_USBPHYACR2);
489 tmp |= PA2_RG_SIF_U2PLL_FORCE_EN;
490 writel(tmp, com + U3P_USBPHYACR2);
492 tmp = readl(com + U3D_U2PHYDCR0);
493 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
494 writel(tmp, com + U3D_U2PHYDCR0);
496 tmp = readl(com + U3D_U2PHYDCR0);
497 tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
498 writel(tmp, com + U3D_U2PHYDCR0);
500 tmp = readl(com + U3P_U2PHYDTM0);
501 tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM;
502 writel(tmp, com + U3P_U2PHYDTM0);
506 tmp = readl(com + U3P_USBPHYACR6);
507 tmp &= ~PA6_RG_U2_BC11_SW_EN; /* DP/DM BC1.1 path Disable */
508 tmp &= ~PA6_RG_U2_SQTH;
509 tmp |= PA6_RG_U2_SQTH_VAL(2);
510 writel(tmp, com + U3P_USBPHYACR6);
521 u32 tmp;
523 tmp = readl(com + U3P_U2PHYDTM0);
524 tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK);
525 writel(tmp, com + U3P_U2PHYDTM0);
528 tmp = readl(com + U3P_USBPHYACR6);
529 tmp |= PA6_RG_U2_OTG_VBUSCMP_EN;
530 writel(tmp, com + U3P_USBPHYACR6);
532 tmp = readl(com + U3P_U2PHYDTM1);
533 tmp |= P2C_RG_VBUSVALID | P2C_RG_AVALID;
534 tmp &= ~P2C_RG_SESSEND;
535 writel(tmp, com + U3P_U2PHYDTM1);
538 tmp = readl(com + U3D_U2PHYDCR0);
539 tmp |= P2C_RG_SIF_U2PLL_FORCE_ON;
540 writel(tmp, com + U3D_U2PHYDCR0);
542 tmp = readl(com + U3P_U2PHYDTM0);
543 tmp |= P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM;
544 writel(tmp, com + U3P_U2PHYDTM0);
555 u32 tmp;
557 tmp = readl(com + U3P_U2PHYDTM0);
558 tmp &= ~(P2C_RG_XCVRSEL | P2C_RG_DATAIN);
559 writel(tmp, com + U3P_U2PHYDTM0);
562 tmp = readl(com + U3P_USBPHYACR6);
563 tmp &= ~PA6_RG_U2_OTG_VBUSCMP_EN;
564 writel(tmp, com + U3P_USBPHYACR6);
566 tmp = readl(com + U3P_U2PHYDTM1);
567 tmp &= ~(P2C_RG_VBUSVALID | P2C_RG_AVALID);
568 tmp |= P2C_RG_SESSEND;
569 writel(tmp, com + U3P_U2PHYDTM1);
572 tmp = readl(com + U3P_U2PHYDTM0);
573 tmp &= ~(P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM);
574 writel(tmp, com + U3P_U2PHYDTM0);
576 tmp = readl(com + U3D_U2PHYDCR0);
577 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
578 writel(tmp, com + U3D_U2PHYDCR0);
590 u32 tmp;
593 tmp = readl(com + U3D_U2PHYDCR0);
594 tmp &= ~P2C_RG_SIF_U2PLL_FORCE_ON;
595 writel(tmp, com + U3D_U2PHYDCR0);
597 tmp = readl(com + U3P_U2PHYDTM0);
598 tmp &= ~P2C_FORCE_SUSPENDM;
599 writel(tmp, com + U3P_U2PHYDTM0);
608 u32 tmp;
610 tmp = readl(u2_banks->com + U3P_U2PHYDTM1);
613 tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG;
616 tmp |= P2C_FORCE_IDDIG;
617 tmp &= ~P2C_RG_IDDIG;
620 tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG);
625 writel(tmp, u2_banks->com + U3P_U2PHYDTM1);
632 u32 tmp;
637 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG0);
638 tmp &= ~(P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H);
639 tmp |= P3A_RG_XTAL_EXT_PE1H_VAL(0x2) | P3A_RG_XTAL_EXT_PE2H_VAL(0x2);
640 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG0);
643 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG1);
644 tmp &= ~P3A_RG_CLKDRV_AMP;
645 tmp |= P3A_RG_CLKDRV_AMP_VAL(0x4);
646 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG1);
648 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0);
649 tmp &= ~P3A_RG_CLKDRV_OFF;
650 tmp |= P3A_RG_CLKDRV_OFF_VAL(0x1);
651 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
654 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG20);
655 tmp &= ~P3A_RG_PLL_DELTA1_PE2H;
656 tmp |= P3A_RG_PLL_DELTA1_PE2H_VAL(0x3c);
657 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG20);
659 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG25);
660 tmp &= ~P3A_RG_PLL_DELTA_PE2H;
661 tmp |= P3A_RG_PLL_DELTA_PE2H_VAL(0x36);
662 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG25);
665 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG5);
666 tmp &= ~(P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H);
667 tmp |= P3A_RG_PLL_BR_PE2H_VAL(0x1) | P3A_RG_PLL_IC_PE2H_VAL(0x1);
668 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG5);
670 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG4);
671 tmp &= ~(P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H);
672 tmp |= P3A_RG_PLL_BC_PE2H_VAL(0x3);
673 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG4);
675 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG6);
676 tmp &= ~P3A_RG_PLL_IR_PE2H;
677 tmp |= P3A_RG_PLL_IR_PE2H_VAL(0x2);
678 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG6);
680 tmp = readl(u3_banks->phya + U3P_U3_PHYA_DA_REG7);
681 tmp &= ~P3A_RG_PLL_BP_PE2H;
682 tmp |= P3A_RG_PLL_BP_PE2H_VAL(0xa);
683 writel(tmp, u3_banks->phya + U3P_U3_PHYA_DA_REG7);
686 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET1);
687 tmp &= ~P3D_RG_RXDET_STB2_SET;
688 tmp |= P3D_RG_RXDET_STB2_SET_VAL(0x10);
689 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET1);
691 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RXDET2);
692 tmp &= ~P3D_RG_RXDET_STB2_SET_P3;
693 tmp |= P3D_RG_RXDET_STB2_SET_P3_VAL(0x10);
694 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RXDET2);
705 u32 tmp;
707 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD);
708 tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
709 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD);
711 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE);
712 tmp &= ~(P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD);
713 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE);
721 u32 tmp;
723 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD);
724 tmp |= P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST;
725 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD);
727 tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE);
728 tmp |= P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD;
729 writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLE);
737 u32 tmp;
740 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL6);
741 tmp &= ~(RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK);
742 tmp |= RG_CDR_BIRLTR_GEN1_VAL(0x6) | RG_CDR_BC_GEN1_VAL(0x1a);
743 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL6);
745 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL4);
746 tmp &= ~RG_CDR_BIRLTD0_GEN1_MSK;
747 tmp |= RG_CDR_BIRLTD0_GEN1_VAL(0x18);
748 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL4);
750 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL5);
751 tmp &= ~RG_CDR_BIRLTD0_GEN3_MSK;
752 tmp |= RG_CDR_BIRLTD0_GEN3_VAL(0x06);
753 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL5);
755 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL4);
756 tmp &= ~(RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK);
757 tmp |= RG_CDR_BICLTR_GEN1_VAL(0x0c) | RG_CDR_BR_GEN2_VAL(0x07);
758 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL4);
760 tmp = readl(phyd + PHYD_CTRL_SIGNAL_MODE4);
761 tmp &= ~(RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK);
762 tmp |= RG_CDR_BICLTD0_GEN1_VAL(0x08) | RG_CDR_BICLTD1_GEN1_VAL(0x02);
763 writel(tmp, phyd + PHYD_CTRL_SIGNAL_MODE4);
765 tmp = readl(phyd + PHYD_DESIGN_OPTION2);
766 tmp &= ~RG_LOCK_CNT_SEL_MSK;
767 tmp |= RG_LOCK_CNT_SEL_VAL(0x02);
768 writel(tmp, phyd + PHYD_DESIGN_OPTION2);
770 tmp = readl(phyd + PHYD_DESIGN_OPTION9);
771 tmp &= ~(RG_T2_MIN_MSK | RG_TG_MIN_MSK |
773 tmp |= RG_T2_MIN_VAL(0x12) | RG_TG_MIN_VAL(0x04) |
775 writel(tmp, phyd + PHYD_DESIGN_OPTION9);
777 tmp = readl(phyd + ANA_RG_CTRL_SIGNAL1);
778 tmp &= ~RG_IDRV_0DB_GEN1_MSK;
779 tmp |= RG_IDRV_0DB_GEN1_VAL(0x20);
780 writel(tmp, phyd + ANA_RG_CTRL_SIGNAL1);
782 tmp = readl(phyd + ANA_EQ_EYE_CTRL_SIGNAL1);
783 tmp &= ~RG_EQ_DLEQ_LFI_GEN1_MSK;
784 tmp |= RG_EQ_DLEQ_LFI_GEN1_VAL(0x03);
785 writel(tmp, phyd + ANA_EQ_EYE_CTRL_SIGNAL1);
873 u32 tmp;
876 tmp = readl(com + U3P_U2PHYBC12C);
877 tmp |= P2C_RG_CHGDT_EN; /* BC1.2 path Enable */
878 writel(tmp, com + U3P_U2PHYBC12C);
882 tmp = readl(com + U3P_USBPHYACR5);
883 tmp &= ~PA5_RG_U2_HSTX_SRCTRL;
884 tmp |= PA5_RG_U2_HSTX_SRCTRL_VAL(instance->eye_src);
885 writel(tmp, com + U3P_USBPHYACR5);
889 tmp = readl(com + U3P_USBPHYACR1);
890 tmp &= ~PA1_RG_VRT_SEL;
891 tmp |= PA1_RG_VRT_SEL_VAL(instance->eye_vrt);
892 writel(tmp, com + U3P_USBPHYACR1);
896 tmp = readl(com + U3P_USBPHYACR1);
897 tmp &= ~PA1_RG_TERM_SEL;
898 tmp |= PA1_RG_TERM_SEL_VAL(instance->eye_term);
899 writel(tmp, com + U3P_USBPHYACR1);
903 tmp = readl(com + U3P_USBPHYACR1);
904 tmp &= ~PA1_RG_INTR_CAL;
905 tmp |= PA1_RG_INTR_CAL_VAL(instance->intr);
906 writel(tmp, com + U3P_USBPHYACR1);
910 tmp = readl(com + U3P_USBPHYACR6);
911 tmp &= ~PA6_RG_U2_DISCTH;
912 tmp |= PA6_RG_U2_DISCTH_VAL(instance->discth);
913 writel(tmp, com + U3P_USBPHYACR6);