Lines Matching refs:hdmi_phy
112 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
114 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
115 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
116 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3, RG_HDMITX_MHLCK_EN);
117 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
119 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
121 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
122 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
129 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
131 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_TXDIV_EN);
132 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_LPF_EN);
134 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_EN);
136 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_BIAS_EN);
137 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
138 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON1, RG_HDMITX_PLL_AUTOK_EN);
145 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
147 hdmi_phy->pll_rate = rate;
159 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
166 dev_dbg(hdmi_phy->dev, "%s: %lu Hz, parent: %lu Hz\n", __func__,
180 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
182 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON0, RG_HDMITX_PLL_POSDIV);
183 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
186 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
188 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
191 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON1,
193 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON0,
199 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,
203 hdmi_ibias = hdmi_phy->ibias;
205 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
209 hdmi_ibias = hdmi_phy->ibias_up;
211 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON4,
220 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON3,
223 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6,
224 (hdmi_phy->drv_imp_clk << DRV_IMP_CLK_SHIFT) |
225 (hdmi_phy->drv_imp_d2 << DRV_IMP_D2_SHIFT) |
226 (hdmi_phy->drv_imp_d1 << DRV_IMP_D1_SHIFT) |
227 (hdmi_phy->drv_imp_d0 << DRV_IMP_D0_SHIFT),
230 mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON5,
245 struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
247 return hdmi_phy->pll_rate;
258 static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)
260 mtk_hdmi_phy_set_bits(hdmi_phy, HDMI_CON3,
266 static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)
268 mtk_hdmi_phy_clear_bits(hdmi_phy, HDMI_CON3,