Lines Matching refs:lane
128 * A lane is described by the following bitfields:
180 unsigned lane;
188 .lane = _lane, \
198 .lane = _lane, \
207 /* lane 0 */
212 /* lane 1 */
219 /* lane 2 */
227 /* lane 3 */
234 /* lane 4 */
245 /* lane 5 */
272 unsigned long lane, unsigned long mode)
277 arm_smccc_smc(function, phys, lane, mode, 0, 0, 0, 0, &res);
290 static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port,
304 if (conf->lane == lane &&
320 static inline int mvebu_comphy_get_mux(int lane, int port,
323 return mvebu_comphy_get_mode(false, lane, port, mode, submode);
326 static inline int mvebu_comphy_get_fw_mode(int lane, int port,
329 return mvebu_comphy_get_mode(true, lane, port, mode, submode);
332 static int mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane)
334 struct mvebu_comphy_priv *priv = lane->priv;
337 regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val);
340 regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val);
343 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
352 switch (lane->submode) {
374 "unsupported comphy submode (%d) on lane %d\n",
375 lane->submode,
376 lane->id);
380 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
382 if (lane->submode == PHY_INTERFACE_MODE_RXAUI) {
385 switch (lane->id) {
396 "RXAUI is not supported on comphy lane %d\n",
397 lane->id);
405 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
409 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
412 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
415 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
421 regmap_read(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), &val);
423 regmap_write(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), val);
426 val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));
428 if (lane->submode == PHY_INTERFACE_MODE_10GBASER)
430 writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));
433 val = readl(priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id));
438 writel(val, priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id));
440 val = readl(priv->base + MVEBU_COMPHY_LOOPBACK(lane->id));
443 writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id));
448 static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane)
450 struct mvebu_comphy_priv *priv = lane->priv;
454 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
458 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));
461 readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id),
471 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
473 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
476 readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id),
482 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
484 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
491 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
492 struct mvebu_comphy_priv *priv = lane->priv;
496 err = mvebu_comphy_ethernet_init_reset(lane);
500 val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
503 writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
505 val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
507 writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
509 regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val);
512 regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val);
514 val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
517 writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
519 return mvebu_comphy_init_plls(lane);
524 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
525 struct mvebu_comphy_priv *priv = lane->priv;
529 err = mvebu_comphy_ethernet_init_reset(lane);
533 val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
536 writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
538 val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
540 writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
542 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
544 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
546 val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
548 writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
550 val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
553 writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
555 val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
561 writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
563 val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id));
565 writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id));
567 val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
570 writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
572 return mvebu_comphy_init_plls(lane);
577 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
578 struct mvebu_comphy_priv *priv = lane->priv;
582 err = mvebu_comphy_ethernet_init_reset(lane);
586 val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
589 writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
591 val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
593 writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));
596 val = readl(priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id));
598 writel(val, priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id));
600 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
602 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));
605 val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
607 writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id));
609 val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
614 writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));
616 val = readl(priv->base + MVEBU_COMPHY_GEN1_S2(lane->id));
619 writel(val, priv->base + MVEBU_COMPHY_GEN1_S2(lane->id));
621 val = readl(priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id));
624 writel(val, priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id));
627 val = readl(priv->base + MVEBU_COMPHY_IMP_CAL(lane->id));
631 writel(val, priv->base + MVEBU_COMPHY_IMP_CAL(lane->id));
633 val = readl(priv->base + MVEBU_COMPHY_GEN1_S5(lane->id));
635 writel(val, priv->base + MVEBU_COMPHY_GEN1_S5(lane->id));
637 val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
647 writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));
649 val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id));
651 writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id));
653 val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
656 writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));
658 val = readl(priv->base + MVEBU_COMPHY_GEN1_S3(lane->id));
660 writel(val, priv->base + MVEBU_COMPHY_GEN1_S3(lane->id));
663 val = readl(priv->base + MVEBU_COMPHY_TRAINING5(lane->id));
666 writel(val, priv->base + MVEBU_COMPHY_TRAINING5(lane->id));
669 val = readl(priv->base + MVEBU_COMPHY_TRAINING0(lane->id));
671 writel(val, priv->base + MVEBU_COMPHY_TRAINING0(lane->id));
673 val = readl(priv->base + MVEBU_COMPHY_TX_PRESET(lane->id));
676 writel(val, priv->base + MVEBU_COMPHY_TX_PRESET(lane->id));
678 val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id));
680 writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id));
682 val = readl(priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id));
685 writel(val, priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id));
687 val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id));
690 writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id));
692 val = readl(priv->base + MVEBU_COMPHY_DME(lane->id));
694 writel(val, priv->base + MVEBU_COMPHY_DME(lane->id));
696 val = readl(priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id));
698 writel(val, priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id));
700 val = readl(priv->base + MVEBU_SP_CALIB(lane->id));
704 writel(val, priv->base + MVEBU_SP_CALIB(lane->id));
706 writel(val, priv->base + MVEBU_SP_CALIB(lane->id));
709 val = readl(priv->base + MVEBU_COMPHY_EXT_SELV(lane->id));
712 writel(val, priv->base + MVEBU_COMPHY_EXT_SELV(lane->id));
714 return mvebu_comphy_init_plls(lane);
719 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
720 struct mvebu_comphy_priv *priv = lane->priv;
724 mux = mvebu_comphy_get_mux(lane->id, lane->port,
725 lane->mode, lane->submode);
730 val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));
734 val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));
735 val |= mux << MVEBU_COMPHY_SELECTOR_PHY(lane->id);
738 switch (lane->submode) {
754 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
756 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
763 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
764 struct mvebu_comphy_priv *priv = lane->priv;
769 fw_mode = mvebu_comphy_get_fw_mode(lane->id, lane->port,
770 lane->mode, lane->submode);
775 switch (lane->mode) {
777 switch (lane->submode) {
779 dev_dbg(priv->dev, "set lane %d to RXAUI mode\n",
780 lane->id);
784 dev_dbg(priv->dev, "set lane %d to 1000BASE-X mode\n",
785 lane->id);
789 dev_dbg(priv->dev, "set lane %d to 2500BASE-X mode\n",
790 lane->id);
794 dev_dbg(priv->dev, "set lane %d to 10GBASE-R mode\n",
795 lane->id);
800 lane->submode);
803 fw_param = COMPHY_FW_PARAM_ETH(fw_mode, lane->port, fw_speed);
807 dev_dbg(priv->dev, "set lane %d to USB3 mode\n", lane->id);
808 fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);
811 dev_dbg(priv->dev, "set lane %d to SATA mode\n", lane->id);
812 fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);
815 dev_dbg(priv->dev, "set lane %d to PCIe mode (x%d)\n", lane->id,
816 lane->submode);
817 fw_param = COMPHY_FW_PARAM_PCIE(fw_mode, lane->port,
818 lane->submode);
821 dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode);
825 ret = mvebu_comphy_smc(COMPHY_SIP_POWER_ON, priv->cp_phys, lane->id,
836 lane->id, lane->mode, ret);
846 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
851 if (mvebu_comphy_get_fw_mode(lane->id, lane->port, mode, submode) < 0)
854 lane->mode = mode;
855 lane->submode = submode;
858 if (mode == PHY_MODE_PCIE && !lane->submode)
859 lane->submode = 1;
866 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
867 struct mvebu_comphy_priv *priv = lane->priv;
870 val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
874 writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));
877 val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));
881 val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));
889 struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
890 struct mvebu_comphy_priv *priv = lane->priv;
894 lane->id, 0);
912 struct mvebu_comphy_lane *lane;
922 lane = phy_get_drvdata(phy);
923 lane->port = args->args[0];
1028 struct mvebu_comphy_lane *lane;
1044 lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);
1045 if (!lane) {
1058 lane->priv = priv;
1059 lane->mode = PHY_MODE_INVALID;
1060 lane->submode = PHY_INTERFACE_MODE_NA;
1061 lane->id = val;
1062 lane->port = -1;
1063 phy_set_drvdata(phy, lane);