Lines Matching defs:lane
58 unsigned int lane;
67 .lane = _lane, \
81 /* lane 0 */
88 /* lane 1 */
95 /* lane 2 */
110 static int mvebu_a3700_comphy_smc(unsigned long function, unsigned long lane,
116 arm_smccc_smc(function, lane, mode, 0, 0, 0, 0, 0, &res);
129 static int mvebu_a3700_comphy_get_fw_mode(int lane, int port,
140 if (mvebu_a3700_comphy_modes[i].lane == lane &&
156 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
162 fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port, mode,
165 dev_err(lane->dev, "invalid COMPHY mode\n");
170 lane->mode = mode;
171 lane->submode = submode;
178 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
183 fw_mode = mvebu_a3700_comphy_get_fw_mode(lane->id, lane->port,
184 lane->mode, lane->submode);
186 dev_err(lane->dev, "invalid COMPHY mode\n");
190 switch (lane->mode) {
192 dev_dbg(lane->dev, "set lane %d to USB3 host mode\n", lane->id);
196 dev_dbg(lane->dev, "set lane %d to SATA mode\n", lane->id);
200 switch (lane->submode) {
202 dev_dbg(lane->dev, "set lane %d to SGMII mode\n",
203 lane->id);
204 fw_param = COMPHY_FW_NET(fw_mode, lane->port,
208 dev_dbg(lane->dev, "set lane %d to HS SGMII mode\n",
209 lane->id);
210 fw_param = COMPHY_FW_NET(fw_mode, lane->port,
214 dev_err(lane->dev, "unsupported PHY submode (%d)\n",
215 lane->submode);
220 dev_dbg(lane->dev, "set lane %d to PCIe mode\n", lane->id);
221 fw_param = COMPHY_FW_PCIE(fw_mode, lane->port,
226 dev_err(lane->dev, "unsupported PHY mode (%d)\n", lane->mode);
230 ret = mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_ON, lane->id, fw_param);
232 dev_err(lane->dev,
240 struct mvebu_a3700_comphy_lane *lane = phy_get_drvdata(phy);
242 return mvebu_a3700_comphy_smc(COMPHY_SIP_POWER_OFF, lane->id, 0);
255 struct mvebu_a3700_comphy_lane *lane;
265 lane = phy_get_drvdata(phy);
266 lane->port = args->args[0];
277 struct mvebu_a3700_comphy_lane *lane;
294 lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);
295 if (!lane) {
307 lane->dev = &pdev->dev;
308 lane->mode = PHY_MODE_INVALID;
309 lane->submode = PHY_INTERFACE_MODE_NA;
310 lane->id = lane_id;
311 lane->port = -1;
312 phy_set_drvdata(phy, lane);