Lines Matching refs:base

110 	void __iomem *base;
113 static unsigned int u2o_get(void __iomem *base, unsigned int offset)
115 return readl_relaxed(base + offset);
118 static void u2o_set(void __iomem *base, unsigned int offset,
123 reg = readl_relaxed(base + offset);
125 writel_relaxed(reg, base + offset);
126 readl_relaxed(base + offset);
129 static void u2o_clear(void __iomem *base, unsigned int offset,
134 reg = readl_relaxed(base + offset);
136 writel_relaxed(reg, base + offset);
137 readl_relaxed(base + offset);
143 void __iomem *base = mmp3_usb_phy->base;
146 u2o_clear(base, USB2_PLL_REG0, (USB2_PLL_FBDIV_MASK_MMP3
148 u2o_set(base, USB2_PLL_REG0,
152 u2o_clear(base, USB2_PLL_REG0, USB2_PLL_REFDIV_MASK_MMP3_B0
154 u2o_set(base, USB2_PLL_REG0,
162 u2o_clear(base, USB2_PLL_REG1, USB2_PLL_PU_PLL_MASK
166 u2o_set(base, USB2_PLL_REG1, 1 << USB2_PLL_PU_PLL_SHIFT_MMP3
172 u2o_clear(base, USB2_TX_REG0, USB2_TX_IMPCAL_VTH_MASK_MMP3);
173 u2o_set(base, USB2_TX_REG0, 2 << USB2_TX_IMPCAL_VTH_SHIFT_MMP3);
175 u2o_clear(base, USB2_TX_REG1, USB2_TX_VDD12_MASK_MMP3
178 u2o_set(base, USB2_TX_REG1, 3 << USB2_TX_VDD12_SHIFT_MMP3
182 u2o_clear(base, USB2_TX_REG2, 3 << USB2_TX_DRV_SLEWRATE_SHIFT);
183 u2o_set(base, USB2_TX_REG2, 2 << USB2_TX_DRV_SLEWRATE_SHIFT);
185 u2o_clear(base, USB2_RX_REG0, USB2_RX_SQ_THRESH_MASK_MMP3);
186 u2o_set(base, USB2_RX_REG0, 0xa << USB2_RX_SQ_THRESH_SHIFT_MMP3);
188 u2o_set(base, USB2_ANA_REG1, 0x1 << USB2_ANA_PU_ANA_SHIFT_MMP3);
190 u2o_set(base, USB2_OTG_REG0, 0x1 << USB2_OTG_PU_OTG_SHIFT_MMP3);
198 void __iomem *base = mmp3_usb_phy->base;
214 u2o_set(base, USB2_PLL_REG1, 1 << USB2_PLL_VCOCAL_START_SHIFT_MMP3);
216 u2o_set(base, USB2_TX_REG0, 1 << USB2_TX_RCAL_START_SHIFT_MMP3);
218 u2o_clear(base, USB2_TX_REG0, 1 << USB2_TX_RCAL_START_SHIFT_MMP3);
222 while ((u2o_get(base, USB2_PLL_REG1) & USB2_PLL_READY_MASK_MMP3) == 0) {
258 mmp3_usb_phy->base = devm_ioremap_resource(dev, resource);
259 if (IS_ERR(mmp3_usb_phy->base)) {
261 return PTR_ERR(mmp3_usb_phy->base);