Lines Matching refs:lane
46 struct a38x_comphy_lane lane[MAX_A38X_COMPHY];
58 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable)
60 struct a38x_comphy *priv = lane->priv;
66 conf |= BIT(lane->port);
68 conf &= ~BIT(lane->port);
73 static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane,
78 val = readl_relaxed(lane->base + offset) & ~mask;
79 writel(val | value, lane->base + offset);
82 static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane,
85 a38x_comphy_set_reg(lane, COMPHY_CFG1,
91 static int a38x_comphy_poll(struct a38x_comphy_lane *lane,
97 ret = readl_relaxed_poll_timeout_atomic(lane->base + offset, val,
102 dev_err(lane->priv->dev,
103 "comphy%u: timed out waiting for status\n", lane->n);
114 struct a38x_comphy_lane *lane = phy_get_drvdata(phy);
135 a38x_set_conf(lane, false);
137 a38x_comphy_set_speed(lane, gen, gen);
139 ret = a38x_comphy_poll(lane, COMPHY_STAT1,
146 a38x_set_conf(lane, true);
159 struct a38x_comphy_lane *lane;
170 lane = phy_get_drvdata(phy);
171 if (lane->port >= 0)
174 lane->port = args->args[0];
176 val = readl_relaxed(lane->priv->base + COMPHY_SELECTOR);
177 val = (val >> (4 * lane->n)) & 0xf;
179 if (!gbe_mux[lane->n][lane->port] ||
180 val != gbe_mux[lane->n][lane->port]) {
181 dev_warn(lane->priv->dev,
182 "comphy%u: not configured for GBE\n", lane->n);
228 if (val >= MAX_A38X_COMPHY || priv->lane[val].base) {
239 priv->lane[val].base = base + 0x28 * val;
240 priv->lane[val].priv = priv;
241 priv->lane[val].n = val;
242 priv->lane[val].port = -1;
243 phy_set_drvdata(phy, &priv->lane[val]);