Lines Matching refs:ret
145 int ret;
147 ret = phy_cfg(iphy);
148 if (ret)
149 return ret;
160 int ret;
162 ret = intel_cbphy_pcie_refclk_cfg(iphy, true);
163 if (ret) {
165 return ret;
183 int ret;
185 ret = intel_cbphy_pcie_refclk_cfg(iphy, false);
186 if (ret) {
188 return ret;
206 int ret;
231 ret = regmap_write(cbphy->hsiocfg, REG_COMBO_MODE(cbphy->bid), cb_mode);
232 if (ret)
233 dev_err(dev, "Failed to set ComboPhy mode: %d\n", ret);
235 return ret;
255 int ret;
258 ret = clk_prepare_enable(cbphy->core_clk);
259 if (ret) {
261 return ret;
264 ret = clk_set_rate(cbphy->core_clk, cbphy->clk_rate);
265 if (ret) {
273 ret = intel_cbphy_set_mode(cbphy);
274 if (ret)
278 ret = intel_cbphy_iphy_enable(iphy, true);
279 if (ret) {
284 ret = reset_control_deassert(iphy->app_rst);
285 if (ret) {
299 return ret;
305 int ret;
307 ret = reset_control_assert(iphy->app_rst);
308 if (ret) {
311 return ret;
314 ret = intel_cbphy_iphy_enable(iphy, false);
315 if (ret) {
317 return ret;
333 int ret;
336 ret = intel_cbphy_iphy_cfg(iphy, intel_cbphy_iphy_power_on);
337 if (ret)
341 ret = intel_cbphy_iphy_cfg(iphy, intel_cbphy_pcie_en_pad_refclk);
342 if (ret)
351 return ret;
358 int ret;
363 ret = intel_cbphy_iphy_cfg(iphy, intel_cbphy_pcie_dis_pad_refclk);
364 if (ret)
368 ret = intel_cbphy_iphy_cfg(iphy, intel_cbphy_iphy_power_off);
373 return ret;
381 int val, ret, id;
392 ret = readl_poll_timeout(cr_base + CR_ADDR(PCS_XF_RX_ADAPT_ACK, id),
394 if (ret)
403 return ret;
412 int ret;
417 ret = PTR_ERR(cbphy->core_clk);
418 if (ret != -EPROBE_DEFER)
419 dev_err(dev, "Get clk failed:%d!\n", ret);
420 return ret;
425 ret = PTR_ERR(cbphy->core_rst);
426 if (ret != -EPROBE_DEFER)
427 dev_err(dev, "Get core reset control err: %d!\n", ret);
428 return ret;
433 ret = PTR_ERR(cbphy->phy_rst);
434 if (ret != -EPROBE_DEFER)
435 dev_err(dev, "Get PHY reset control err: %d!\n", ret);
436 return ret;
441 ret = PTR_ERR(cbphy->iphy[0].app_rst);
442 if (ret != -EPROBE_DEFER)
443 dev_err(dev, "Get phy0 reset control err: %d!\n", ret);
444 return ret;
449 ret = PTR_ERR(cbphy->iphy[1].app_rst);
450 if (ret != -EPROBE_DEFER)
451 dev_err(dev, "Get phy1 reset control err: %d!\n", ret);
452 return ret;
468 ret = fwnode_property_get_reference_args(fwnode, "intel,syscfg", NULL,
470 if (ret < 0)
471 return ret;
477 ret = fwnode_property_get_reference_args(fwnode, "intel,hsio", NULL, 1,
479 if (ret < 0)
480 return ret;
486 ret = fwnode_property_read_u32_array(fwnode, "intel,phy-mode", &val, 1);
487 if (ret)
488 return ret;
589 int ret;
598 ret = intel_cbphy_fwnode_parse(cbphy);
599 if (ret)
600 return ret;