Lines Matching refs:val
324 /* Set RX PPM val center frequency */
402 unsigned int val;
407 val = 0x0;
408 val |= (0xc << OOB_CTRL1_BURST_MAX_SHIFT);
409 val |= (0x4 << OOB_CTRL1_BURST_MIN_SHIFT);
410 val |= (0x9 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
411 val |= (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
412 brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
413 val = 0x0;
414 val |= (0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
415 val |= (0x2 << OOB_CTRL2_BURST_CNT_SHIFT);
416 val |= (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
417 brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
420 val = NS2_PLL1_ACTRL2_MAGIC;
421 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
422 val = NS2_PLL1_ACTRL3_MAGIC;
423 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
424 val = NS2_PLL1_ACTRL4_MAGIC;
425 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
442 val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
444 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
464 unsigned int val, try;
474 val = 0x0;
475 val |= (0x0f << OOB_CTRL1_BURST_MAX_SHIFT);
476 val |= (0x06 << OOB_CTRL1_BURST_MIN_SHIFT);
477 val |= (0x0f << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
478 val |= (0x06 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
479 brcm_sata_phy_wr(port, oob_bank, OOB_CTRL1, 0x0, val);
481 val = 0x0;
482 val |= (0x2e << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
483 val |= (0x02 << OOB_CTRL2_BURST_CNT_SHIFT);
484 val |= (0x16 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
485 brcm_sata_phy_wr(port, oob_bank, OOB_CTRL2, 0x0, val);
495 val = PLLCONTROL_0_FREQ_DET_RESTART | PLLCONTROL_0_FREQ_MONITOR;
497 ~val, val);
498 val = PLLCONTROL_0_SEQ_START;
500 ~val, 0);
503 ~val, val);
508 val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
510 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
536 unsigned int val, try;
539 val = SR_PLL1_ACTRL2_MAGIC;
540 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
541 val = SR_PLL1_ACTRL3_MAGIC;
542 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
543 val = SR_PLL1_ACTRL4_MAGIC;
544 brcm_sata_phy_wr(port, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
547 val = SR_PLL0_ACTRL6_MAGIC;
548 brcm_sata_phy_wr(port, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val);
553 val = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
555 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
561 if ((val & BLOCK0_XGXSSTATUS_PLL_LOCK) == 0) {
572 val = ((0xc << OOB_CTRL1_BURST_MAX_SHIFT) |
576 brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
577 val = ((0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT) |
580 brcm_sata_phy_wr(port, OOB_REG_BANK, OOB_CTRL2, 0x0, val);