Lines Matching defs:tmp
211 u32 tmp;
219 tmp = readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
220 tmp = (tmp & msk) | value;
221 writel(tmp, pcb_base + SATA_PCB_REG_OFFSET(ofs));
246 u32 tmp;
249 tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC;
250 brcm_sata_phy_wr(port, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
260 tmp = STB_FMAX_VAL_SSC;
262 tmp = STB_FMAX_VAL_DEFAULT;
266 ~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp);
274 u32 tmp = 0, reg = 0;
282 tmp = AEQ_CONTROL1_ENABLE | AEQ_CONTROL1_FREEZE;
287 tmp = AEQ_FRC_EQ_FORCE | AEQ_FRC_EQ_FORCE_VAL;
290 tmp |= port->rxaeq_val << AEQ_FRC_EQ_VAL_SHIFT;
294 brcm_sata_phy_wr(port, AEQRX_REG_BANK_0, reg, ~tmp, tmp);
295 brcm_sata_phy_wr(port, AEQRX_REG_BANK_1, reg, ~tmp, tmp);
309 u32 tmp, value;
318 tmp = AEQ_FRC_EQ_FORCE_VAL | AEQ_FRC_EQ_FORCE;
320 ~(tmp | AEQ_RFZ_FRC_VAL |
322 tmp | 32 << AEQ_FRC_EQ_VAL_SHIFT);
333 tmp = RXPMD_G_CDR_PROP_BW_MASK << RXPMD_G1_CDR_PROP_BW_SHIFT |
344 brcm_sata_phy_wr(port, RXPMD_REG_BANK, RXPMD_RX_CDR_CDR_PROP_BW, ~tmp,
348 tmp = RXPMD_G_CDR_ACQ_INT_BW_MASK << RXPMD_G1_CDR_ACQ_INT_BW_SHIFT |
358 ~tmp, value);
361 tmp = RXPMD_G_CDR_LOCK_INT_BW_MASK << RXPMD_G1_CDR_LOCK_INT_BW_SHIFT |
371 ~tmp, value);
374 tmp = RXPMD_MON_CORRECT_EN | RXPMD_MON_MARGIN_VAL_MASK;
380 ~tmp, RXPMD_MON_CORRECT_EN | value);
589 u32 tmp;
620 tmp = brcm_sata_phy_rd(port, BLOCK0_REG_BANK,
622 if (tmp & BLOCK0_XGXSSTATUS_PLL_LOCK)
673 u32 tmp = BIT(8);
676 ~tmp, tmp);