Lines Matching refs:pmu_dev
108 void (*write_evttype)(struct xgene_pmu_dev *pmu_dev, int idx, u32 val);
109 void (*write_agentmsk)(struct xgene_pmu_dev *pmu_dev, u32 val);
110 void (*write_agent1msk)(struct xgene_pmu_dev *pmu_dev, u32 val);
111 void (*enable_counter)(struct xgene_pmu_dev *pmu_dev, int idx);
112 void (*disable_counter)(struct xgene_pmu_dev *pmu_dev, int idx);
113 void (*enable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx);
114 void (*disable_counter_int)(struct xgene_pmu_dev *pmu_dev, int idx);
115 void (*reset_counters)(struct xgene_pmu_dev *pmu_dev);
116 void (*start_counters)(struct xgene_pmu_dev *pmu_dev);
117 void (*stop_counters)(struct xgene_pmu_dev *pmu_dev);
141 struct xgene_pmu_dev *pmu_dev;
610 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(dev_get_drvdata(dev));
612 return cpumap_print_to_pagebuf(true, buf, &pmu_dev->parent->cpu);
695 static int get_next_avail_cntr(struct xgene_pmu_dev *pmu_dev)
699 cntr = find_first_zero_bit(pmu_dev->cntr_assign_mask,
700 pmu_dev->max_counters);
701 if (cntr == pmu_dev->max_counters)
703 set_bit(cntr, pmu_dev->cntr_assign_mask);
708 static void clear_avail_cntr(struct xgene_pmu_dev *pmu_dev, int cntr)
710 clear_bit(cntr, pmu_dev->cntr_assign_mask);
734 static inline u64 xgene_pmu_read_counter32(struct xgene_pmu_dev *pmu_dev,
737 return readl(pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));
740 static inline u64 xgene_pmu_read_counter64(struct xgene_pmu_dev *pmu_dev,
752 hi = xgene_pmu_read_counter32(pmu_dev, 2 * idx + 1);
753 lo = xgene_pmu_read_counter32(pmu_dev, 2 * idx);
754 } while (hi != xgene_pmu_read_counter32(pmu_dev, 2 * idx + 1));
760 xgene_pmu_write_counter32(struct xgene_pmu_dev *pmu_dev, int idx, u64 val)
762 writel(val, pmu_dev->inf->csr + PMU_PMEVCNTR0 + (4 * idx));
766 xgene_pmu_write_counter64(struct xgene_pmu_dev *pmu_dev, int idx, u64 val)
774 xgene_pmu_write_counter32(pmu_dev, 2 * idx, cnt_lo);
775 xgene_pmu_write_counter32(pmu_dev, 2 * idx + 1, cnt_hi);
779 xgene_pmu_write_evttype(struct xgene_pmu_dev *pmu_dev, int idx, u32 val)
781 writel(val, pmu_dev->inf->csr + PMU_PMEVTYPER0 + (4 * idx));
785 xgene_pmu_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val)
787 writel(val, pmu_dev->inf->csr + PMU_PMAMR0);
791 xgene_pmu_v3_write_agentmsk(struct xgene_pmu_dev *pmu_dev, u32 val) { }
794 xgene_pmu_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val)
796 writel(val, pmu_dev->inf->csr + PMU_PMAMR1);
800 xgene_pmu_v3_write_agent1msk(struct xgene_pmu_dev *pmu_dev, u32 val) { }
803 xgene_pmu_enable_counter(struct xgene_pmu_dev *pmu_dev, int idx)
807 val = readl(pmu_dev->inf->csr + PMU_PMCNTENSET);
809 writel(val, pmu_dev->inf->csr + PMU_PMCNTENSET);
813 xgene_pmu_disable_counter(struct xgene_pmu_dev *pmu_dev, int idx)
817 val = readl(pmu_dev->inf->csr + PMU_PMCNTENCLR);
819 writel(val, pmu_dev->inf->csr + PMU_PMCNTENCLR);
823 xgene_pmu_enable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx)
827 val = readl(pmu_dev->inf->csr + PMU_PMINTENSET);
829 writel(val, pmu_dev->inf->csr + PMU_PMINTENSET);
833 xgene_pmu_disable_counter_int(struct xgene_pmu_dev *pmu_dev, int idx)
837 val = readl(pmu_dev->inf->csr + PMU_PMINTENCLR);
839 writel(val, pmu_dev->inf->csr + PMU_PMINTENCLR);
842 static inline void xgene_pmu_reset_counters(struct xgene_pmu_dev *pmu_dev)
846 val = readl(pmu_dev->inf->csr + PMU_PMCR);
848 writel(val, pmu_dev->inf->csr + PMU_PMCR);
851 static inline void xgene_pmu_start_counters(struct xgene_pmu_dev *pmu_dev)
855 val = readl(pmu_dev->inf->csr + PMU_PMCR);
857 writel(val, pmu_dev->inf->csr + PMU_PMCR);
860 static inline void xgene_pmu_stop_counters(struct xgene_pmu_dev *pmu_dev)
864 val = readl(pmu_dev->inf->csr + PMU_PMCR);
866 writel(val, pmu_dev->inf->csr + PMU_PMCR);
871 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu);
872 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
873 int enabled = bitmap_weight(pmu_dev->cntr_assign_mask,
874 pmu_dev->max_counters);
879 xgene_pmu->ops->start_counters(pmu_dev);
884 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(pmu);
885 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
887 xgene_pmu->ops->stop_counters(pmu_dev);
892 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
919 event->cpu = cpumask_first(&pmu_dev->parent->cpu);
949 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
950 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
952 xgene_pmu->ops->write_evttype(pmu_dev, GET_CNTR(event),
954 xgene_pmu->ops->write_agentmsk(pmu_dev, ~((u32)GET_AGENTID(event)));
955 if (pmu_dev->inf->type == PMU_TYPE_IOB)
956 xgene_pmu->ops->write_agent1msk(pmu_dev,
959 xgene_pmu->ops->enable_counter(pmu_dev, GET_CNTR(event));
960 xgene_pmu->ops->enable_counter_int(pmu_dev, GET_CNTR(event));
965 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
966 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
968 xgene_pmu->ops->disable_counter(pmu_dev, GET_CNTR(event));
969 xgene_pmu->ops->disable_counter_int(pmu_dev, GET_CNTR(event));
974 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
975 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
987 xgene_pmu->ops->write_counter(pmu_dev, hw->idx, val);
992 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
993 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
999 new_raw_count = xgene_pmu->ops->read_counter(pmu_dev, GET_CNTR(event));
1005 delta = (new_raw_count - prev_raw_count) & pmu_dev->max_period;
1017 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
1018 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
1032 xgene_pmu->ops->write_counter(pmu_dev, GET_CNTR(event),
1060 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
1066 hw->idx = get_next_avail_cntr(pmu_dev);
1071 pmu_dev->pmu_counter_event[hw->idx] = event;
1081 struct xgene_pmu_dev *pmu_dev = to_pmu_dev(event->pmu);
1087 clear_avail_cntr(pmu_dev, GET_CNTR(event));
1090 pmu_dev->pmu_counter_event[hw->idx] = NULL;
1093 static int xgene_init_perf(struct xgene_pmu_dev *pmu_dev, char *name)
1097 if (pmu_dev->parent->version == PCP_PMU_V3)
1098 pmu_dev->max_period = PMU_V3_CNT_MAX_PERIOD;
1100 pmu_dev->max_period = PMU_CNT_MAX_PERIOD;
1102 xgene_pmu = pmu_dev->parent;
1104 pmu_dev->max_counters = 1;
1106 pmu_dev->max_counters = PMU_MAX_COUNTERS;
1109 pmu_dev->pmu = (struct pmu) {
1110 .attr_groups = pmu_dev->attr_groups,
1124 xgene_pmu->ops->stop_counters(pmu_dev);
1125 xgene_pmu->ops->reset_counters(pmu_dev);
1127 return perf_pmu_register(&pmu_dev->pmu, name, -1);
1141 ctx->pmu_dev = pmu;
1192 static void _xgene_pmu_isr(int irq, struct xgene_pmu_dev *pmu_dev)
1194 struct xgene_pmu *xgene_pmu = pmu_dev->parent;
1195 void __iomem *csr = pmu_dev->inf->csr;
1199 xgene_pmu->ops->stop_counters(pmu_dev);
1218 struct perf_event *event = pmu_dev->pmu_counter_event[idx];
1229 xgene_pmu->ops->start_counters(pmu_dev);
1257 _xgene_pmu_isr(irq, ctx->pmu_dev);
1262 _xgene_pmu_isr(irq, ctx->pmu_dev);
1267 _xgene_pmu_isr(irq, ctx->pmu_dev);
1272 _xgene_pmu_isr(irq, ctx->pmu_dev);
1818 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1821 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1824 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1827 perf_pmu_migrate_context(&ctx->pmu_dev->pmu, cpu, target);
1955 perf_pmu_unregister(&ctx->pmu_dev->pmu);