Lines Matching defs:reg_base
112 void __iomem *reg_base;
138 smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
139 writel(SMMU_PMCG_CR_ENABLE, smmu_pmu->reg_base + SMMU_PMCG_CR);
160 writel(0, smmu_pmu->reg_base + SMMU_PMCG_CR);
161 writel(0, smmu_pmu->reg_base + SMMU_PMCG_IRQ_CTRL);
175 writel(0xffff, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx));
203 writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENSET0);
208 writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0);
213 writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENSET0);
219 writeq(BIT(idx), smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0);
225 writel(val, smmu_pmu->reg_base + SMMU_PMCG_EVTYPER(idx));
230 writel(val, smmu_pmu->reg_base + SMMU_PMCG_SMR(idx));
682 writeq_relaxed(doorbell, pmu->reg_base + SMMU_PMCG_IRQ_CFG0);
683 writel_relaxed(msg->data, pmu->reg_base + SMMU_PMCG_IRQ_CFG1);
685 pmu->reg_base + SMMU_PMCG_IRQ_CFG2);
695 writeq_relaxed(0, pmu->reg_base + SMMU_PMCG_IRQ_CFG0);
698 if (!(readl(pmu->reg_base + SMMU_PMCG_CFGR) & SMMU_PMCG_CFGR_MSI))
737 smmu_pmu->reg_base + SMMU_PMCG_CNTENCLR0);
739 smmu_pmu->reg_base + SMMU_PMCG_INTENCLR0);
795 smmu_pmu->reg_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res_0);
796 if (IS_ERR(smmu_pmu->reg_base))
797 return PTR_ERR(smmu_pmu->reg_base);
799 cfgr = readl_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CFGR);
807 smmu_pmu->reloc_base = smmu_pmu->reg_base;
814 ceid_64[0] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID0);
815 ceid_64[1] = readq_relaxed(smmu_pmu->reg_base + SMMU_PMCG_CEID1);