Lines Matching refs:xp
688 struct arm_cmn_node *xp = arm_cmn_node_to_xp(dn);
690 u64 reg = readq_relaxed(xp->pmu_base + offset);
848 int wp_idx, xp = arm_cmn_node_to_xp(dn)->logid;
850 val->dtm_count[xp]++;
851 val->occupid[xp] = occupid;
857 val->wp[xp][wp_idx] = CMN_EVENT_WP_COMBINE(event) + 1;
896 int wp_idx, wp_cmb, xp = arm_cmn_node_to_xp(dn)->logid;
898 if (val.dtm_count[xp] == CMN_DTM_NUM_COUNTERS)
901 if (occupid && val.occupid[xp] && occupid != val.occupid[xp])
908 if (val.wp[xp][wp_idx])
911 wp_cmb = val.wp[xp][wp_idx ^ 1];
991 struct arm_cmn_node *xp = arm_cmn_node_to_xp(hw->dn + i);
1000 xp->pmu_config_low &= ~CMN__PMEVCNT_PAIRED(dtm_idx);
1001 writel_relaxed(xp->pmu_config_low, xp->pmu_base + CMN_DTM_PMU_CONFIG);
1043 struct arm_cmn_node *xp = arm_cmn_node_to_xp(dn);
1048 while (xp->pmu_config_low & CMN__PMEVCNT_PAIRED(dtm_idx))
1092 xp->input_sel[dtm_idx] = input_sel;
1094 xp->pmu_config_low &= ~(CMN__PMEVCNT0_GLOBAL_NUM << shift);
1095 xp->pmu_config_low |= FIELD_PREP(CMN__PMEVCNT0_GLOBAL_NUM, dtc_idx) << shift;
1096 xp->pmu_config_low |= CMN__PMEVCNT_PAIRED(dtm_idx);
1097 reg = (u64)le32_to_cpu(xp->pmu_config_high) << 32 | xp->pmu_config_low;
1098 writeq_relaxed(reg, xp->pmu_base + CMN_DTM_PMU_CONFIG);
1234 static void arm_cmn_init_dtm(struct arm_cmn_node *xp)
1239 xp->wp_event[i] = -1;
1240 writeq_relaxed(0, xp->pmu_base + CMN_DTM_WPn_MASK(i));
1241 writeq_relaxed(~0ULL, xp->pmu_base + CMN_DTM_WPn_VAL(i));
1243 xp->pmu_config_low = CMN_DTM_PMU_CONFIG_PMU_EN;
1244 xp->dtc = -1;
1250 struct arm_cmn_node *xp;
1263 xp = arm_cmn_node_to_xp(dn);
1264 xp->dtc = idx;
1379 struct arm_cmn_node *xp = dn++;
1381 arm_cmn_init_node_info(cmn, xp_offset[i], xp);
1382 arm_cmn_init_dtm(xp);
1389 if (xp->id == (1 << 3))
1390 cmn->mesh_x = xp->logid;