Lines Matching refs:reg
84 static inline u32 cb_readl(struct yenta_socket *socket, unsigned reg)
86 u32 val = readl(socket->base + reg);
87 debug("%04x %08x\n", socket, reg, val);
91 static inline void cb_writel(struct yenta_socket *socket, unsigned reg, u32 val)
93 debug("%04x %08x\n", socket, reg, val);
94 writel(val, socket->base + reg);
95 readl(socket->base + reg); /* avoid problems with PCI write posting */
140 static inline u8 exca_readb(struct yenta_socket *socket, unsigned reg)
142 u8 val = readb(socket->base + 0x800 + reg);
143 debug("%04x %02x\n", socket, reg, val);
147 static inline u8 exca_readw(struct yenta_socket *socket, unsigned reg)
150 val = readb(socket->base + 0x800 + reg);
151 val |= readb(socket->base + 0x800 + reg + 1) << 8;
152 debug("%04x %04x\n", socket, reg, val);
156 static inline void exca_writeb(struct yenta_socket *socket, unsigned reg, u8 val)
158 debug("%04x %02x\n", socket, reg, val);
159 writeb(val, socket->base + 0x800 + reg);
160 readb(socket->base + 0x800 + reg); /* PCI write posting... */
163 static void exca_writew(struct yenta_socket *socket, unsigned reg, u16 val)
165 debug("%04x %04x\n", socket, reg, val);
166 writeb(val, socket->base + 0x800 + reg);
167 writeb(val >> 8, socket->base + 0x800 + reg + 1);
170 readb(socket->base + 0x800 + reg);
171 readb(socket->base + 0x800 + reg + 1);
251 u8 reg, old;
252 reg = old = exca_readb(socket, I365_POWER);
253 reg &= ~(I365_VCC_MASK | I365_VPP1_MASK | I365_VPP2_MASK);
259 reg |= I365_VCC_3V;
262 reg |= I365_VCC_5V;
265 reg = 0;
271 reg |= I365_VPP1_5V;
274 reg |= I365_VPP1_12V;
281 reg |= I365_VCC_5V;
284 reg = 0;
289 reg |= I365_VPP1_5V | I365_VPP2_5V;
292 reg |= I365_VPP1_12V | I365_VPP2_12V;
297 if (reg != old)
298 exca_writeb(socket, I365_POWER, reg);
300 u32 reg = 0; /* CB_SC_STPCLK? */
303 reg = CB_SC_VCC_3V;
306 reg = CB_SC_VCC_5V;
309 reg = 0;
314 reg |= CB_SC_VPP_3V;
317 reg |= CB_SC_VPP_5V;
320 reg |= CB_SC_VPP_12V;
323 if (reg != cb_readl(socket, CB_SOCKET_CONTROL))
324 cb_writel(socket, CB_SOCKET_CONTROL, reg);
352 u8 reg;
354 reg = exca_readb(socket, I365_INTCTL) & (I365_RING_ENA | I365_INTR_ENA);
355 reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
356 reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
358 reg |= state->io_irq;
361 exca_writeb(socket, I365_INTCTL, reg);
363 reg = exca_readb(socket, I365_POWER) & (I365_VCC_MASK|I365_VPP1_MASK);
364 reg |= I365_PWR_NORESET;
366 reg |= I365_PWR_AUTO;
368 reg |= I365_PWR_OUT;
369 if (exca_readb(socket, I365_POWER) != reg)
370 exca_writeb(socket, I365_POWER, reg);
373 reg = exca_readb(socket, I365_CSCINT);
374 reg &= I365_CSC_IRQ_MASK;
375 reg |= I365_CSC_DETECT;
378 reg |= I365_CSC_STSCHG;
381 reg |= I365_CSC_BVD1;
383 reg |= I365_CSC_BVD2;
385 reg |= I365_CSC_READY;
387 exca_writeb(socket, I365_CSCINT, reg);
929 u8 reg;
937 reg = exca_readb(socket, I365_CSCINT);
949 exca_writeb(socket, I365_CSCINT, reg);
986 u8 reg = 0;
1001 reg = exca_readb(socket, I365_CSCINT);
1002 exca_writeb(socket, I365_CSCINT, reg | I365_CSC_STSCHG);
1011 exca_writeb(socket, I365_CSCINT, reg);