Lines Matching defs:val
867 u32 val;
870 pci_read_config_dword(dev, reg, &val);
873 if (!(val & 1))
875 base = val & 0xfffc;
911 u32 val;
914 pci_read_config_dword(dev, reg, &val);
917 if (!(val & 1))
921 base = val & 0xfffc;
922 mask = (val >> 16) & 0xfc;
1582 u16 val;
1587 pci_read_config_word(dev, 0xF2, &val);
1588 if (val & 0x8) {
1589 pci_write_config_word(dev, 0xF2, val & (~0x8));
1590 pci_read_config_word(dev, 0xF2, &val);
1591 if (val & 0x8)
1593 val);
1632 u32 val;
1638 val = readl(asus_rcba_base + 0x3418);
1641 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1668 u8 val = 0;
1669 pci_read_config_byte(dev, 0x77, &val);
1670 if (val & 0x10) {
1672 pci_write_config_byte(dev, 0x77, val & ~0x10);
1726 u8 val;
1737 pci_read_config_byte(dev, 0x50, &val);
1738 if (val & 0xc0) {
1739 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1740 pci_read_config_byte(dev, 0x50, &val);
1741 if (val & 0xc0)
1743 val);
3396 u8 val;
3398 rc = pci_read_config_byte(dev, 0x00D0, &val);
3402 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3404 rc = pci_read_config_byte(dev, 0x00D1, &val);
3408 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3820 u32 val;
3839 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3840 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3844 val = ioread32(mmio_base + PCH_PP_STATUS);
3845 if ((val & 0xb0000000) == 0)
4038 u32 val;
4048 val = ioread32be(bar + HINIC_VF_FLR_TYPE);
4049 if (!(val & HINIC_VF_FLR_CAP_BIT)) {
4055 val = ioread32be(bar + HINIC_VF_OP);
4056 val = val | HINIC_VF_FLR_PROC_BIT;
4057 iowrite32be(val, bar + HINIC_VF_OP);
4071 val = ioread32be(bar + HINIC_VF_OP);
4072 if (!(val & HINIC_VF_FLR_PROC_BIT))
4077 val = ioread32be(bar + HINIC_VF_OP);
4078 if (!(val & HINIC_VF_FLR_PROC_BIT))
4081 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val);
5570 u32 val;
5577 pci_read_config_dword(gpu, 0x488, &val);
5578 if (val & BIT(25))
5582 pci_write_config_dword(gpu, 0x488, val | BIT(25));