Lines Matching defs:port

604 static void quirk_io_region(struct pci_dev *dev, int port,
611 	pci_read_config_word(dev, port, &region);
712 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
717 	pci_read_config_dword(dev, port, &devres);
738 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
743 	pci_read_config_dword(dev, port, &devres);
1773 	case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1782 		/* Redirect IDE second PATA port to the right spot */
2405  * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected;
2738  * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
3652  * Root port on some Cavium CN8xxx chips do not successfully complete a bus
4734 	 * peer-to-peer transactions via the root port and each has a unique
4764  * Errata 22)[4].  Per the datasheet[5], root port PCI Device IDs for this
4767  * 0xa290-0xa29f PCI Express Root port #{0-16}
4768  * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4779  * 0x9d10-0x9d1b PCI Express Root port #{1-12}
5118 	 * the UPDCR to disable peer decodes for each port.  This provides the
5180 	pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
5210 	pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
5234 	pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n");
5599  *   Item #36 - Downstream port applies ACS Source Validation to Completions
5602  *   completions received by a downstream port of the PCIe switch from a
5604  *   dropped by ACS Source Validation by the switch downstream port.