Lines Matching refs:pdev
77 static bool dpc_completed(struct pci_dev *pdev)
81 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_STATUS, &status);
85 if (test_bit(PCI_DPC_RECOVERING, &pdev->priv_flags))
93 * @pdev: PCI device
95 * Return true if DPC was triggered for @pdev and has recovered successfully.
99 bool pci_dpc_recovered(struct pci_dev *pdev)
103 if (!pdev->dpc_cap)
110 host = pci_find_host_bridge(pdev->bus);
119 wait_event_timeout(dpc_completed_waitqueue, dpc_completed(pdev),
122 return test_and_clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
126 static int dpc_wait_rp_inactive(struct pci_dev *pdev)
129 u16 cap = pdev->dpc_cap, status;
131 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
135 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
138 pci_warn(pdev, "root port still busy\n");
144 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev)
149 set_bit(PCI_DPC_RECOVERING, &pdev->priv_flags);
155 cap = pdev->dpc_cap;
161 if (!pcie_wait_for_link(pdev, false))
162 pci_info(pdev, "Data Link Layer Link Active not cleared in 1000 msec\n");
164 if (pdev->dpc_rp_extensions && dpc_wait_rp_inactive(pdev)) {
165 clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
170 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
173 if (pci_bridge_wait_for_secondary_bus(pdev, "DPC",
175 clear_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
178 set_bit(PCI_DPC_RECOVERED, &pdev->priv_flags);
182 clear_bit(PCI_DPC_RECOVERING, &pdev->priv_flags);
187 static void dpc_process_rp_pio_error(struct pci_dev *pdev)
189 u16 cap = pdev->dpc_cap, dpc_status, first_error;
193 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, &status);
194 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_MASK, &mask);
195 pci_err(pdev, "rp_pio_status: %#010x, rp_pio_mask: %#010x\n",
198 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SEVERITY, &sev);
199 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_SYSERROR, &syserr);
200 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_EXCEPTION, &exc);
201 pci_err(pdev, "RP PIO severity=%#010x, syserror=%#010x, exception=%#010x\n",
205 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &dpc_status);
210 pci_err(pdev, "[%2d] %s%s\n", i, rp_pio_error_string[i],
214 if (pdev->dpc_rp_log_size < 4)
216 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG,
218 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 4,
220 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 8,
222 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_HEADER_LOG + 12,
224 pci_err(pdev, "TLP Header: %#010x %#010x %#010x %#010x\n",
227 if (pdev->dpc_rp_log_size < 5)
229 pci_read_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG, &log);
230 pci_err(pdev, "RP PIO ImpSpec Log %#010x\n", log);
232 for (i = 0; i < pdev->dpc_rp_log_size - 5; i++) {
233 pci_read_config_dword(pdev,
235 pci_err(pdev, "TLP Prefix Header: dw%d, %#010x\n", i, prefix);
238 pci_write_config_dword(pdev, cap + PCI_EXP_DPC_RP_PIO_STATUS, status);
263 void dpc_process_error(struct pci_dev *pdev)
265 u16 cap = pdev->dpc_cap, status, source, reason, ext_reason;
268 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
269 pci_read_config_word(pdev, cap + PCI_EXP_DPC_SOURCE_ID, &source);
271 pci_info(pdev, "containment event, status:%#06x source:%#06x\n",
276 pci_warn(pdev, "%s detected\n",
285 if (pdev->dpc_rp_extensions && reason == 3 && ext_reason == 0)
286 dpc_process_rp_pio_error(pdev);
288 dpc_get_aer_uncorrect_severity(pdev, &info) &&
289 aer_get_device_error_info(pdev, &info)) {
290 aer_print_error(pdev, &info);
291 pci_aer_clear_nonfatal_status(pdev);
292 pci_aer_clear_fatal_status(pdev);
298 struct pci_dev *pdev = context;
300 dpc_process_error(pdev);
303 pcie_do_recovery(pdev, pci_channel_io_frozen, dpc_reset_link);
310 struct pci_dev *pdev = context;
311 u16 cap = pdev->dpc_cap, status;
313 pci_read_config_word(pdev, cap + PCI_EXP_DPC_STATUS, &status);
318 pci_write_config_word(pdev, cap + PCI_EXP_DPC_STATUS,
325 void pci_dpc_init(struct pci_dev *pdev)
329 pdev->dpc_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
330 if (!pdev->dpc_cap)
333 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
337 pdev->dpc_rp_extensions = true;
338 pdev->dpc_rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
339 if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
340 pci_err(pdev, "RP PIO log size %u is invalid\n",
341 pdev->dpc_rp_log_size);
342 pdev->dpc_rp_log_size = 0;
349 struct pci_dev *pdev = dev->port;
354 if (!pcie_aer_is_native(pdev) && !pcie_ports_dpc_native)
359 "pcie-dpc", pdev);
361 pci_warn(pdev, "request IRQ%d failed: %d\n", dev->irq,
366 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
367 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl);
370 pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl);
371 pci_info(pdev, "enabled with IRQ %d\n", dev->irq);
373 pci_info(pdev, "error containment capabilities: Int Msg #%d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
376 FLAG(cap, PCI_EXP_DPC_CAP_SW_TRIGGER), pdev->dpc_rp_log_size,
379 pci_add_ext_cap_save_buffer(pdev, PCI_EXT_CAP_ID_DPC, sizeof(u16));
385 struct pci_dev *pdev = dev->port;
388 pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl);
390 pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl);