Lines Matching defs:upstream
267 /* Check upstream component if bit Slot Clock Configuration is 1 */
300 /* Configure upstream component */
409 /* Check upstream direction L0s latency */
538 /* Program Common_Mode_Restore_Time in upstream device */
587 * Re-read upstream/downstream components' register state after
760 u32 upstream = 0, dwstream = 0;
780 /* Convert ASPM state to upstream/downstream ASPM register state */
784 upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
786 upstream |= PCI_EXP_LNKCTL_ASPM_L1;
796 * upstream component first and then downstream, and vice
800 pcie_config_aspm_dev(parent, upstream);
804 pcie_config_aspm_dev(parent, upstream);
924 * We allocate pcie_link_state for the component on the upstream
946 * upstream links also because capable state of them can be
1031 /* Recheck latencies and configure upstream links */
1206 * Relies on the upstream bridge's link_state being valid. The link_state