Lines Matching defs:downstream
51 struct pci_dev *downstream; /* Downstream component, function 0 */
73 * Endpoint acceptable latencies. A pcie downstream port only
262 /* Check downstream component if bit Slot Clock Configuration is 1 */
292 /* Configure downstream component, all functions */
414 /* Check downstream direction L0s latency */
470 struct pci_dev *child = link->downstream, *parent = link->pdev;
503 * downstream devices report (via LTR) that they can tolerate at
560 struct pci_dev *child = link->downstream, *parent = link->pdev;
587 * Re-read upstream/downstream components' register state after
702 struct pci_dev *child = link->downstream, *parent = link->pdev;
761 struct pci_dev *child = link->downstream, *parent = link->pdev;
780 /* Convert ASPM state to upstream/downstream ASPM register state */
796 * upstream component first and then downstream, and vice
868 link->downstream = pci_function_0(pdev->subordinate);
873 * the root ports entirely, in which case a downstream port on
910 * @pdev: the root port or switch downstream port
926 * downstream port.
1017 * link->downstream is a pointer to the pci_dev of function 0. If
1019 * so we can't use link->downstream again. Free the link state to
1041 /* @pdev: the root port or switch downstream port */