Lines Matching refs:dev
59 struct pci_dev *dev;
64 static void pci_dev_d3_sleep(struct pci_dev *dev)
66 unsigned int delay = dev->d3hot_delay;
238 * @dev: the PCI device to test
255 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path,
279 if (dev->devfn != PCI_DEVFN(slot, func)) {
290 dev = pci_upstream_bridge(dev);
291 if (!dev) {
310 ret = (seg == pci_domain_nr(dev->bus) &&
311 bus == dev->bus->number &&
312 dev->devfn == PCI_DEVFN(slot, func));
321 * @dev: the PCI device to test
349 static int pci_dev_str_match(struct pci_dev *dev, const char *p,
372 if ((!vendor || vendor == dev->vendor) &&
373 (!device || device == dev->device) &&
375 subsystem_vendor == dev->subsystem_vendor) &&
377 subsystem_device == dev->subsystem_device))
384 ret = pci_dev_str_match_path(dev, p, &p);
431 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
433 return __pci_find_next_cap(dev->bus, dev->devfn,
460 * @dev: PCI device to query
477 int pci_find_capability(struct pci_dev *dev, int cap)
481 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
483 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
519 * @dev: PCI device to query
528 int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
537 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
543 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
561 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
571 * @dev: PCI device to query
583 int pci_find_ext_capability(struct pci_dev *dev, int cap)
585 return pci_find_next_ext_capability(dev, 0, cap);
591 * @dev: PCI device to query
598 u64 pci_get_dsn(struct pci_dev *dev)
604 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DSN);
614 pci_read_config_dword(dev, pos, &dword);
616 pci_read_config_dword(dev, pos + 4, &dword);
623 static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
633 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
636 rc = pci_read_config_byte(dev, pos + 3, &cap);
643 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
652 * @dev: PCI device to query
663 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
665 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
671 * @dev: PCI device to query
680 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
684 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
686 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
695 * @dev: PCI device structure contains resources to be searched
701 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
704 const struct pci_bus *bus = dev->bus;
738 * @dev: PCI device to query
745 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
750 struct resource *r = &dev->resource[i];
762 * @dev: the PCI device to operate on
768 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
778 pci_read_config_word(dev, pos, &status);
800 * @dev: the PCI device
804 static void pci_disable_acs_redir(struct pci_dev *dev)
816 ret = pci_dev_str_match(dev, p, &p);
837 if (!pci_dev_specific_disable_acs_redir(dev))
840 pos = dev->acs_cap;
842 pci_warn(dev, "cannot disable ACS redirect for this hardware as it does not have ACS capabilities\n");
846 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
851 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
853 pci_info(dev, "disabled ACS redirect\n");
858 * @dev: the PCI device
860 static void pci_std_enable_acs(struct pci_dev *dev)
866 pos = dev->acs_cap;
870 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
871 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
886 if (dev->external_facing || dev->untrusted)
889 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
894 * @dev: the PCI device
896 static void pci_enable_acs(struct pci_dev *dev)
901 if (!pci_dev_specific_enable_acs(dev))
904 pci_std_enable_acs(dev);
914 pci_disable_acs_redir(dev);
919 * @dev: PCI device to have its BARs restored
924 static void pci_restore_bars(struct pci_dev *dev)
929 pci_update_resource(dev, i);
943 static inline bool platform_pci_power_manageable(struct pci_dev *dev)
945 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
948 static inline int platform_pci_set_power_state(struct pci_dev *dev,
951 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
954 static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
956 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
959 static inline void platform_pci_refresh_power_state(struct pci_dev *dev)
962 pci_platform_pm->refresh_state(dev);
965 static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
968 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
971 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable)
974 pci_platform_pm->set_wakeup(dev, enable) : -ENODEV;
977 static inline bool platform_pci_need_resume(struct pci_dev *dev)
979 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
982 static inline bool platform_pci_bridge_d3(struct pci_dev *dev)
985 return pci_platform_pm->bridge_d3(dev);
992 * @dev: PCI device to handle.
1002 static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
1008 if (dev->current_state == state)
1011 if (!dev->pm_cap)
1023 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
1024 && dev->current_state > state) {
1025 pci_err(dev, "invalid power transition (from %s to %s)\n",
1026 pci_power_name(dev->current_state),
1032 if ((state == PCI_D1 && !dev->d1_support)
1033 || (state == PCI_D2 && !dev->d2_support))
1036 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1038 pci_err(dev, "can't change power state from %s to %s (config space inaccessible)\n",
1039 pci_power_name(dev->current_state),
1049 switch (dev->current_state) {
1069 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
1075 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
1076 pci_dev_d3_sleep(dev);
1077 else if (state == PCI_D2 || dev->current_state == PCI_D2)
1080 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1081 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1082 if (dev->current_state != state)
1083 pci_info_ratelimited(dev, "refused to change power state from %s to %s\n",
1084 pci_power_name(dev->current_state),
1101 pci_restore_bars(dev);
1103 if (dev->bus->self)
1104 pcie_aspm_pm_state_change(dev->bus->self);
1111 * @dev: PCI device to handle.
1121 void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
1123 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
1124 !pci_device_is_present(dev)) {
1125 dev->current_state = PCI_D3cold;
1126 } else if (dev->pm_cap) {
1129 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1130 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1132 dev->current_state = state;
1138 * @dev: Target PCI device.
1143 void pci_refresh_power_state(struct pci_dev *dev)
1145 if (platform_pci_power_manageable(dev))
1146 platform_pci_refresh_power_state(dev);
1148 pci_update_current_state(dev, dev->current_state);
1153 * @dev: PCI device to handle.
1156 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
1160 if (platform_pci_power_manageable(dev)) {
1161 error = platform_pci_set_power_state(dev, state);
1163 pci_update_current_state(dev, state);
1167 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
1168 dev->current_state = PCI_D0;
1182 pm_request_resume(&pci_dev->dev);
1196 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
1213 pci_read_config_dword(dev, PCI_COMMAND, &id);
1216 pci_warn(dev, "not ready %dms after %s; giving up\n",
1222 pci_info(dev, "not ready %dms after %s; waiting\n",
1227 pci_read_config_dword(dev, PCI_COMMAND, &id);
1231 pci_info(dev, "ready %dms after %s\n", delay - 1,
1239 * @dev: PCI device to power up
1241 int pci_power_up(struct pci_dev *dev)
1243 pci_platform_power_transition(dev, PCI_D0);
1250 if (dev->runtime_d3cold) {
1256 pci_wakeup_bus(dev->subordinate);
1259 return pci_raw_set_power_state(dev, PCI_D0);
1264 * @dev: Device to handle
1267 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
1271 dev->current_state = state;
1288 * @dev: PCI device to handle.
1303 int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1312 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
1323 if (dev->current_state == state)
1327 return pci_power_up(dev);
1333 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
1340 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
1343 if (pci_platform_power_transition(dev, state))
1348 pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
1356 * @dev: PCI device to be suspended
1363 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
1367 if (!dev->pm_cap)
1370 ret = platform_pci_choose_state(dev);
1384 pci_info(dev, "unrecognized suspend event %d\n",
1406 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
1408 return _pci_find_saved_cap(dev, cap, false);
1411 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1413 return _pci_find_saved_cap(dev, cap, true);
1416 static int pci_save_pcie_state(struct pci_dev *dev)
1422 if (!pci_is_pcie(dev))
1425 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1427 pci_err(dev, "buffer not found in %s\n", __func__);
1432 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1433 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1434 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1435 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1436 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1437 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1438 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
1443 static void pci_restore_pcie_state(struct pci_dev *dev)
1449 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
1454 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1455 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1456 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1457 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1458 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1459 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1460 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
1463 static int pci_save_pcix_state(struct pci_dev *dev)
1468 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1472 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1474 pci_err(dev, "buffer not found in %s\n", __func__);
1478 pci_read_config_word(dev, pos + PCI_X_CMD,
1484 static void pci_restore_pcix_state(struct pci_dev *dev)
1490 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1491 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1496 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
1499 static void pci_save_ltr_state(struct pci_dev *dev)
1505 if (!pci_is_pcie(dev))
1508 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1512 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1514 pci_err(dev, "no suspend buffer for LTR; ASPM issues possible after resume\n");
1519 pci_read_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, cap++);
1520 pci_read_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, cap++);
1523 static void pci_restore_ltr_state(struct pci_dev *dev)
1529 save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_LTR);
1530 ltr = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
1535 pci_write_config_word(dev, ltr + PCI_LTR_MAX_SNOOP_LAT, *cap++);
1536 pci_write_config_word(dev, ltr + PCI_LTR_MAX_NOSNOOP_LAT, *cap++);
1542 * @dev: PCI device that we're dealing with
1544 int pci_save_state(struct pci_dev *dev)
1549 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
1550 pci_dbg(dev, "saving config space at offset %#x (reading %#x)\n",
1551 i * 4, dev->saved_config_space[i]);
1553 dev->state_saved = true;
1555 i = pci_save_pcie_state(dev);
1559 i = pci_save_pcix_state(dev);
1563 pci_save_ltr_state(dev);
1564 pci_save_dpc_state(dev);
1565 pci_save_aer_state(dev);
1566 return pci_save_vc_state(dev);
1657 * @dev: PCI device that we're dealing with
1659 void pci_restore_state(struct pci_dev *dev)
1661 if (!dev->state_saved)
1668 pci_restore_ltr_state(dev);
1670 pci_restore_pcie_state(dev);
1671 pci_restore_pasid_state(dev);
1672 pci_restore_pri_state(dev);
1673 pci_restore_ats_state(dev);
1674 pci_restore_vc_state(dev);
1675 pci_restore_rebar_state(dev);
1676 pci_restore_dpc_state(dev);
1678 pci_aer_clear_status(dev);
1679 pci_restore_aer_state(dev);
1681 pci_restore_config_space(dev);
1683 pci_restore_pcix_state(dev);
1684 pci_restore_msi_state(dev);
1687 pci_enable_acs(dev);
1688 pci_restore_iov_state(dev);
1690 dev->state_saved = false;
1702 * @dev: PCI device that we're dealing with
1706 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1713 if (!dev->state_saved)
1718 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
1725 memcpy(state->config_space, dev->saved_config_space,
1729 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
1742 * @dev: PCI device that we're dealing with
1745 int pci_load_saved_state(struct pci_dev *dev,
1750 dev->state_saved = false;
1755 memcpy(dev->saved_config_space, state->config_space,
1762 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
1771 dev->state_saved = true;
1779 * @dev: PCI device that we're dealing with
1782 int pci_load_and_free_saved_state(struct pci_dev *dev,
1785 int ret = pci_load_saved_state(dev, *state);
1792 int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1794 return pci_enable_resources(dev, bars);
1797 static int do_pci_enable_device(struct pci_dev *dev, int bars)
1804 err = pci_set_power_state(dev, PCI_D0);
1808 bridge = pci_upstream_bridge(dev);
1812 err = pcibios_enable_device(dev, bars);
1815 pci_fixup_device(pci_fixup_enable, dev);
1817 if (dev->msi_enabled || dev->msix_enabled)
1820 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1822 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1824 pci_write_config_word(dev, PCI_COMMAND,
1833 * @dev: PCI device to be resumed
1838 int pci_reenable_device(struct pci_dev *dev)
1840 if (pci_is_enabled(dev))
1841 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1846 static void pci_enable_bridge(struct pci_dev *dev)
1851 bridge = pci_upstream_bridge(dev);
1855 if (pci_is_enabled(dev)) {
1856 if (!dev->is_busmaster)
1857 pci_set_master(dev);
1861 retval = pci_enable_device(dev);
1863 pci_err(dev, "Error enabling bridge (%d), continuing\n",
1865 pci_set_master(dev);
1868 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
1880 pci_update_current_state(dev, dev->current_state);
1882 if (atomic_inc_return(&dev->enable_cnt) > 1)
1885 bridge = pci_upstream_bridge(dev);
1891 if (dev->resource[i].flags & flags)
1894 if (dev->resource[i].flags & flags)
1897 err = do_pci_enable_device(dev, bars);
1899 atomic_dec(&dev->enable_cnt);
1905 * @dev: PCI device to be initialized
1911 int pci_enable_device_io(struct pci_dev *dev)
1913 return pci_enable_device_flags(dev, IORESOURCE_IO);
1919 * @dev: PCI device to be initialized
1925 int pci_enable_device_mem(struct pci_dev *dev)
1927 return pci_enable_device_flags(dev, IORESOURCE_MEM);
1933 * @dev: PCI device to be initialized
1942 int pci_enable_device(struct pci_dev *dev)
1944 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
1965 struct pci_dev *dev = to_pci_dev(gendev);
1969 if (dev->msi_enabled)
1970 pci_disable_msi(dev);
1971 if (dev->msix_enabled)
1972 pci_disable_msix(dev);
1976 pci_release_region(dev, i);
1979 pci_clear_mwi(dev);
1982 pci_intx(dev, this->orig_intx);
1985 pci_disable_device(dev);
1992 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1999 return devres_get(&pdev->dev, new_dr, NULL, NULL);
2005 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
2055 * pcibios_add_device - provide arch specific hooks when adding device dev
2056 * @dev: the PCI device being added
2062 int __weak pcibios_add_device(struct pci_dev *dev)
2069 * device dev
2070 * @dev: the PCI device being released
2076 void __weak pcibios_release_device(struct pci_dev *dev) {}
2079 * pcibios_disable_device - disable arch specific PCI resources for device dev
2080 * @dev: the PCI device to disable
2086 void __weak pcibios_disable_device(struct pci_dev *dev) {}
2099 static void do_pci_disable_device(struct pci_dev *dev)
2103 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
2106 pci_write_config_word(dev, PCI_COMMAND, pci_command);
2109 pcibios_disable_device(dev);
2114 * @dev: PCI device to disable
2119 void pci_disable_enabled_device(struct pci_dev *dev)
2121 if (pci_is_enabled(dev))
2122 do_pci_disable_device(dev);
2127 * @dev: PCI device to be disabled
2135 void pci_disable_device(struct pci_dev *dev)
2139 dr = find_pci_dr(dev);
2143 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
2146 if (atomic_dec_return(&dev->enable_cnt) != 0)
2149 do_pci_disable_device(dev);
2151 dev->is_busmaster = 0;
2156 * pcibios_set_pcie_reset_state - set reset state for device dev
2157 * @dev: the PCIe device reset
2163 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
2170 * pci_set_pcie_reset_state - set reset state for device dev
2171 * @dev: the PCIe device reset
2176 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
2178 return pcibios_set_pcie_reset_state(dev, state);
2182 void pcie_clear_device_status(struct pci_dev *dev)
2186 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &sta);
2187 pcie_capability_write_word(dev, PCI_EXP_DEVSTA, sta);
2192 * @dev: PCIe root port or event collector.
2194 void pcie_clear_root_pme_status(struct pci_dev *dev)
2196 pcie_capability_set_dword(dev, PCI_EXP_RTSTA, PCI_EXP_RTSTA_PME);
2201 * @dev: Device to check.
2207 bool pci_check_pme_status(struct pci_dev *dev)
2213 if (!dev->pm_cap)
2216 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
2217 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
2229 pci_write_config_word(dev, pmcsr_pos, pmcsr);
2236 * @dev: Device to handle.
2239 * Check if @dev has generated PME and queue a resume request for it in that
2242 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
2244 if (pme_poll_reset && dev->pme_poll)
2245 dev->pme_poll = false;
2247 if (pci_check_pme_status(dev)) {
2248 pci_wakeup_event(dev);
2249 pm_request_resume(&dev->dev);
2267 * @dev: PCI device to handle.
2270 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
2272 if (!dev->pm_cap)
2275 return !!(dev->pme_support & (1 << state));
2285 if (pme_dev->dev->pme_poll) {
2288 bridge = pme_dev->dev->bus->self;
2300 if (pme_dev->dev->current_state == PCI_D3cold)
2303 pci_pme_wakeup(pme_dev->dev, NULL);
2315 static void __pci_pme_active(struct pci_dev *dev, bool enable)
2319 if (!dev->pme_support)
2322 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2328 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2333 * @dev: PCI device to update.
2335 void pci_pme_restore(struct pci_dev *dev)
2339 if (!dev->pme_support)
2342 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2343 if (dev->wakeup_prepared) {
2350 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
2355 * @dev: PCI device to handle.
2361 void pci_pme_active(struct pci_dev *dev, bool enable)
2363 __pci_pme_active(dev, enable);
2385 if (dev->pme_poll) {
2391 pci_warn(dev, "can't enable PME#\n");
2394 pme_dev->dev = dev;
2405 if (pme_dev->dev == dev) {
2415 pci_dbg(dev, "PME# %s\n", enable ? "enabled" : "disabled");
2421 * @dev: PCI device affected
2438 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable)
2449 if (!pci_power_manageable(dev))
2453 if (!!enable == !!dev->wakeup_prepared)
2472 if (pci_pme_capable(dev, state) || pci_pme_capable(dev, PCI_D3cold))
2473 pci_pme_active(dev, true);
2476 error = platform_pci_set_wakeup(dev, true);
2480 dev->wakeup_prepared = true;
2482 platform_pci_set_wakeup(dev, false);
2483 pci_pme_active(dev, false);
2484 dev->wakeup_prepared = false;
2501 if (enable && !device_may_wakeup(&pci_dev->dev))
2510 * @dev: PCI device to prepare
2522 int pci_wake_from_d3(struct pci_dev *dev, bool enable)
2524 return pci_pme_capable(dev, PCI_D3cold) ?
2525 pci_enable_wake(dev, PCI_D3cold, enable) :
2526 pci_enable_wake(dev, PCI_D3hot, enable);
2531 * pci_target_state - find an appropriate low power state for a given PCI dev
2532 * @dev: PCI device
2535 * Use underlying platform code to find a supported low power state for @dev.
2536 * If the platform can't manage @dev, return the deepest state from which it
2539 static pci_power_t pci_target_state(struct pci_dev *dev, bool wakeup)
2543 if (platform_pci_power_manageable(dev)) {
2547 pci_power_t state = platform_pci_choose_state(dev);
2555 if (pci_no_d1d2(dev))
2565 if (!dev->pm_cap)
2573 if (dev->current_state == PCI_D3cold)
2576 if (wakeup && dev->pme_support) {
2583 while (state && !(dev->pme_support & (1 << state)))
2588 else if (dev->pme_support & 1)
2598 * @dev: Device to handle.
2604 int pci_prepare_to_sleep(struct pci_dev *dev)
2606 bool wakeup = device_may_wakeup(&dev->dev);
2607 pci_power_t target_state = pci_target_state(dev, wakeup);
2613 pci_enable_wake(dev, target_state, wakeup);
2615 error = pci_set_power_state(dev, target_state);
2618 pci_enable_wake(dev, target_state, false);
2627 * @dev: Device to handle.
2631 int pci_back_from_sleep(struct pci_dev *dev)
2633 pci_enable_wake(dev, PCI_D0, false);
2634 return pci_set_power_state(dev, PCI_D0);
2640 * @dev: PCI device being suspended.
2642 * Prepare @dev to generate wake-up events at run time and put it into a low
2645 int pci_finish_runtime_suspend(struct pci_dev *dev)
2650 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev));
2654 dev->runtime_d3cold = target_state == PCI_D3cold;
2656 __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
2658 error = pci_set_power_state(dev, target_state);
2661 pci_enable_wake(dev, target_state, false);
2662 dev->runtime_d3cold = false;
2670 * @dev: Device to check.
2676 bool pci_dev_run_wake(struct pci_dev *dev)
2678 struct pci_bus *bus = dev->bus;
2680 if (!dev->pme_support)
2684 if (!pci_pme_capable(dev, pci_target_state(dev, true)))
2687 if (device_can_wakeup(&dev->dev))
2693 if (device_can_wakeup(&bridge->dev))
2718 struct device *dev = &pci_dev->dev;
2721 if (!pm_runtime_suspended(dev) || platform_pci_need_resume(pci_dev))
2724 target_state = pci_target_state(pci_dev, device_may_wakeup(dev));
2749 struct device *dev = &pci_dev->dev;
2751 spin_lock_irq(&dev->power.lock);
2753 if (pm_runtime_suspended(dev) && !device_may_wakeup(dev) &&
2757 spin_unlock_irq(&dev->power.lock);
2770 struct device *dev = &pci_dev->dev;
2775 spin_lock_irq(&dev->power.lock);
2777 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2780 spin_unlock_irq(&dev->power.lock);
2785 struct device *dev = &pdev->dev;
2786 struct device *parent = dev->parent;
2790 pm_runtime_get_noresume(dev);
2795 pm_runtime_barrier(dev);
2802 pm_runtime_resume(dev);
2807 struct device *dev = &pdev->dev;
2808 struct device *parent = dev->parent;
2810 pm_runtime_put(dev);
2906 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2911 dev->no_d3cold || !dev->d3cold_allowed ||
2914 (device_may_wakeup(&dev->dev) &&
2915 !pci_pme_capable(dev, PCI_D3cold)) ||
2918 !pci_power_manageable(dev))
2927 * @dev: PCI device which is changed
2933 void pci_bridge_d3_update(struct pci_dev *dev)
2935 bool remove = !device_is_registered(&dev->dev);
2939 bridge = pci_upstream_bridge(dev);
2959 pci_dev_check_d3cold(dev, &d3cold_ok);
2980 * @dev: PCI device to handle
2986 void pci_d3cold_enable(struct pci_dev *dev)
2988 if (dev->no_d3cold) {
2989 dev->no_d3cold = false;
2990 pci_bridge_d3_update(dev);
2997 * @dev: PCI device to handle
3003 void pci_d3cold_disable(struct pci_dev *dev)
3005 if (!dev->no_d3cold) {
3006 dev->no_d3cold = true;
3007 pci_bridge_d3_update(dev);
3014 * @dev: PCI device to handle.
3016 void pci_pm_init(struct pci_dev *dev)
3022 pm_runtime_forbid(&dev->dev);
3023 pm_runtime_set_active(&dev->dev);
3024 pm_runtime_enable(&dev->dev);
3025 device_enable_async_suspend(&dev->dev);
3026 dev->wakeup_prepared = false;
3028 dev->pm_cap = 0;
3029 dev->pme_support = 0;
3032 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3036 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
3039 pci_err(dev, "unsupported PM cap regs version (%u)\n",
3044 dev->pm_cap = pm;
3045 dev->d3hot_delay = PCI_PM_D3HOT_WAIT;
3046 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
3047 dev->bridge_d3 = pci_bridge_d3_possible(dev);
3048 dev->d3cold_allowed = true;
3050 dev->d1_support = false;
3051 dev->d2_support = false;
3052 if (!pci_no_d1d2(dev)) {
3054 dev->d1_support = true;
3056 dev->d2_support = true;
3058 if (dev->d1_support || dev->d2_support)
3059 pci_info(dev, "supports%s%s\n",
3060 dev->d1_support ? " D1" : "",
3061 dev->d2_support ? " D2" : "");
3066 pci_info(dev, "PME# supported from%s%s%s%s%s\n",
3072 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
3073 dev->pme_poll = true;
3078 device_set_wakeup_capable(&dev->dev, true);
3080 pci_pme_active(dev, false);
3083 pci_read_config_word(dev, PCI_STATUS, &status);
3085 dev->imm_ready = 1;
3088 static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
3111 static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
3115 return &dev->resource[bei];
3119 return &dev->resource[PCI_IOV_RESOURCES +
3123 return &dev->resource[PCI_ROM_RESOURCE];
3129 static int pci_ea_read(struct pci_dev *dev, int offset)
3139 pci_read_config_dword(dev, ent_offset, &dw0);
3160 res = pci_ea_get_resource(dev, bei, prop);
3162 pci_err(dev, "Unsupported EA entry BEI: %u\n", bei);
3166 flags = pci_ea_flags(dev, prop);
3168 pci_err(dev, "Unsupported EA properties: %#x\n", prop);
3173 pci_read_config_dword(dev, ent_offset, &base);
3178 pci_read_config_dword(dev, ent_offset, &max_offset);
3185 pci_read_config_dword(dev, ent_offset, &base_upper);
3204 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
3218 pci_err(dev, "EA Entry crosses address boundary\n");
3223 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n",
3228 res->name = pci_name(dev);
3234 pci_info(dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3237 pci_info(dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
3240 pci_info(dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
3243 pci_info(dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
3251 void pci_ea_init(struct pci_dev *dev)
3259 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
3264 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
3271 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
3276 offset = pci_ea_read(dev, offset);
3288 * @dev: the PCI device
3293 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
3300 pos = pci_find_ext_capability(dev, cap);
3302 pos = pci_find_capability(dev, cap);
3314 pci_add_saved_cap(dev, save_state);
3319 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
3321 return _pci_add_cap_save_buffer(dev, cap, false, size);
3324 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
3326 return _pci_add_cap_save_buffer(dev, cap, true, size);
3331 * @dev: the PCI device
3333 void pci_allocate_cap_save_buffers(struct pci_dev *dev)
3337 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
3340 pci_err(dev, "unable to preallocate PCI Express save buffer\n");
3342 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
3344 pci_err(dev, "unable to preallocate PCI-X save buffer\n");
3346 error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_LTR,
3349 pci_err(dev, "unable to allocate suspend buffer for LTR\n");
3351 pci_allocate_vc_save_buffers(dev);
3354 void pci_free_cap_save_buffers(struct pci_dev *dev)
3359 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
3365 * @dev: the PCI device
3367 * If @dev and its upstream bridge both support ARI, enable ARI in the
3370 void pci_configure_ari(struct pci_dev *dev)
3375 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
3378 bridge = dev->bus->self;
3386 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
3529 * @dev: the PCI device
3531 void pci_acs_init(struct pci_dev *dev)
3533 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
3541 pci_enable_acs(dev);
3654 * @dev: the PCI device
3665 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
3667 struct pci_bus *bus = dev->bus;
3671 if (!pci_is_pcie(dev))
3681 switch (pci_pcie_type(dev)) {
3721 pcie_capability_set_word(dev, PCI_EXP_DEVCTL2,
3729 * @dev: the PCI device
3738 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
3742 if (pci_ari_enabled(dev->bus))
3745 slot = PCI_SLOT(dev->devfn);
3750 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
3754 pin = dev->pin;
3758 while (!pci_is_root_bus(dev->bus)) {
3759 pin = pci_swizzle_interrupt_pin(dev, pin);
3760 dev = dev->bus->self;
3762 *bridge = dev;
3768 * @dev: the PCI device
3774 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
3778 while (!pci_is_root_bus(dev->bus)) {
3779 pin = pci_swizzle_interrupt_pin(dev, pin);
3780 dev = dev->bus->self;
3783 return PCI_SLOT(dev->devfn);
3829 * is explicitly not allowed to map the resource via /dev/mem or
3990 * pci_request_regions_exclusive() will mark the region so that /dev/mem
4117 static void devm_pci_unmap_iospace(struct device *dev, void *ptr)
4126 * @dev: Generic device to remap IO address for
4133 int devm_pci_remap_iospace(struct device *dev, const struct resource *res,
4148 devres_add(dev, ptr);
4157 * @dev: Generic device to remap IO address for
4164 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
4177 devres_add(dev, ptr);
4187 * @dev: generic device to handle the resource for
4200 * base = devm_pci_remap_cfg_resource(&pdev->dev, res);
4204 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
4211 BUG_ON(!dev);
4214 dev_err(dev, "invalid resource\n");
4219 name = res->name ?: dev_name(dev);
4221 if (!devm_request_mem_region(dev, res->start, size, name)) {
4222 dev_err(dev, "can't request region for resource %pR\n", res);
4226 dest_ptr = devm_pci_remap_cfgspace(dev, res->start, size);
4228 dev_err(dev, "ioremap failed for resource %pR\n", res);
4229 devm_release_mem_region(dev, res->start, size);
4237 static void __pci_set_master(struct pci_dev *dev, bool enable)
4241 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
4247 pci_dbg(dev, "%s bus mastering\n",
4249 pci_write_config_word(dev, PCI_COMMAND, cmd);
4251 dev->is_busmaster = enable;
4267 * pcibios_set_master - enable PCI bus-mastering for device dev
4268 * @dev: the PCI device to enable
4274 void __weak pcibios_set_master(struct pci_dev *dev)
4279 if (pci_is_pcie(dev))
4282 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
4290 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
4294 * pci_set_master - enables bus-mastering for device dev
4295 * @dev: the PCI device to enable
4300 void pci_set_master(struct pci_dev *dev)
4302 __pci_set_master(dev, true);
4303 pcibios_set_master(dev);
4308 * pci_clear_master - disables bus-mastering for device dev
4309 * @dev: the PCI device to disable
4311 void pci_clear_master(struct pci_dev *dev)
4313 __pci_set_master(dev, false);
4319 * @dev: the PCI device for which MWI is to be enabled
4327 int pci_set_cacheline_size(struct pci_dev *dev)
4336 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4342 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
4344 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
4348 pci_info(dev, "cache line size of %d is not supported\n",
4357 * @dev: the PCI device for which MWI is enabled
4363 int pci_set_mwi(struct pci_dev *dev)
4371 rc = pci_set_cacheline_size(dev);
4375 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4377 pci_dbg(dev, "enabling Mem-Wr-Inval\n");
4379 pci_write_config_word(dev, PCI_COMMAND, cmd);
4388 * @dev: the PCI device for which MWI is enabled
4394 int pcim_set_mwi(struct pci_dev *dev)
4398 dr = find_pci_dr(dev);
4403 return pci_set_mwi(dev);
4409 * @dev: the PCI device for which MWI is enabled
4416 int pci_try_set_mwi(struct pci_dev *dev)
4421 return pci_set_mwi(dev);
4427 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4428 * @dev: the PCI device to disable
4432 void pci_clear_mwi(struct pci_dev *dev)
4437 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4440 pci_write_config_word(dev, PCI_COMMAND, cmd);
4447 * pci_intx - enables/disables PCI INTx for device dev
4478 static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
4480 struct pci_bus *bus = dev->bus;
4496 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
4515 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
4525 * @dev: the PCI device to operate on
4527 * Check if the device dev has its INTx line asserted, mask it and return
4530 bool pci_check_and_mask_intx(struct pci_dev *dev)
4532 return pci_check_and_set_intx_mask(dev, true);
4538 * @dev: the PCI device to operate on
4540 * Check if the device dev has its INTx line asserted, unmask it if not and
4544 bool pci_check_and_unmask_intx(struct pci_dev *dev)
4546 return pci_check_and_set_intx_mask(dev, false);
4552 * @dev: the PCI device to operate on
4556 int pci_wait_for_pending_transaction(struct pci_dev *dev)
4558 if (!pci_is_pcie(dev))
4561 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
4568 * @dev: device to check
4573 bool pcie_has_flr(struct pci_dev *dev)
4577 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4580 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
4587 * @dev: device to reset
4589 * Initiate a function level reset on @dev. The caller should ensure the
4593 int pcie_flr(struct pci_dev *dev)
4595 if (!pci_wait_for_pending_transaction(dev))
4596 pci_err(dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
4598 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
4600 if (dev->imm_ready)
4610 return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
4614 static int pci_af_flr(struct pci_dev *dev, int probe)
4619 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
4623 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET)
4626 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
4638 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
4640 pci_err(dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
4642 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
4644 if (dev->imm_ready)
4655 return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
4660 * @dev: Device to reset.
4663 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4670 * by default (i.e. unless the @dev's d3hot_delay field has a different value).
4673 static int pci_pm_reset(struct pci_dev *dev, int probe)
4677 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
4680 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
4687 if (dev->current_state != PCI_D0)
4692 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4693 pci_dev_d3_sleep(dev);
4697 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
4698 pci_dev_d3_sleep(dev);
4700 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS);
4791 * @dev: PCI bridge
4806 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type,
4812 if (pci_dev_is_disconnected(dev))
4815 if (!pci_is_bridge(dev))
4826 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) {
4832 delay = pci_bus_max_d3cold_delay(dev->subordinate);
4838 child = pci_dev_get(list_first_entry(&dev->subordinate->devices,
4846 if (!pci_is_pcie(dev)) {
4847 pci_dbg(dev, "waiting %d ms for secondary bus\n", 1000 + delay);
4869 if (!pcie_downstream_port(dev))
4872 if (pcie_get_speed_cap(dev) <= PCIE_SPEED_5_0GT) {
4873 pci_dbg(dev, "waiting %d ms for downstream link\n", delay);
4876 pci_dbg(dev, "waiting %d ms for downstream link, after activation\n",
4878 if (!pcie_wait_for_link_delay(dev, true, delay)) {
4880 pci_info(dev, "Data Link Layer Link Active not set in 1000 msec\n");
4893 void pci_reset_secondary_bus(struct pci_dev *dev)
4897 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
4899 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4908 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
4911 void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
4913 pci_reset_secondary_bus(dev);
4918 * @dev: Bridge device
4923 int pci_bridge_secondary_bus_reset(struct pci_dev *dev)
4925 pcibios_reset_secondary_bus(dev);
4927 return pci_bridge_wait_for_secondary_bus(dev, "bus reset",
4932 static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
4936 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
4937 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4940 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
4941 if (pdev != dev)
4947 return pci_bridge_secondary_bus_reset(dev->bus->self);
4965 static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
4967 if (dev->multifunction || dev->subordinate || !dev->slot ||
4968 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
4971 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
4974 static void pci_dev_lock(struct pci_dev *dev)
4977 device_lock(&dev->dev);
4978 pci_cfg_access_lock(dev);
4982 static int pci_dev_trylock(struct pci_dev *dev)
4984 if (device_trylock(&dev->dev)) {
4985 if (pci_cfg_access_trylock(dev))
4987 device_unlock(&dev->dev);
4993 static void pci_dev_unlock(struct pci_dev *dev)
4995 pci_cfg_access_unlock(dev);
4996 device_unlock(&dev->dev);
4999 static void pci_dev_save_and_disable(struct pci_dev *dev)
5002 dev->driver ? dev->driver->err_handler : NULL;
5005 * dev->driver->err_handler->reset_prepare() is protected against
5010 err_handler->reset_prepare(dev);
5017 pci_set_power_state(dev, PCI_D0);
5019 pci_save_state(dev);
5027 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
5030 static void pci_dev_restore(struct pci_dev *dev)
5033 dev->driver ? dev->driver->err_handler : NULL;
5035 pci_restore_state(dev);
5038 * dev->driver->err_handler->reset_done() is protected against
5043 err_handler->reset_done(dev);
5048 * the @dev mutex lock.
5049 * @dev: PCI device to reset
5066 int __pci_reset_function_locked(struct pci_dev *dev)
5080 rc = pci_dev_specific_reset(dev, 0);
5083 if (pcie_has_flr(dev)) {
5084 rc = pcie_flr(dev);
5088 rc = pci_af_flr(dev, 0);
5091 rc = pci_pm_reset(dev, 0);
5094 rc = pci_dev_reset_slot_function(dev, 0);
5097 return pci_parent_bus_reset(dev, 0);
5103 * @dev: PCI device to reset
5112 int pci_probe_reset_function(struct pci_dev *dev)
5118 rc = pci_dev_specific_reset(dev, 1);
5121 if (pcie_has_flr(dev))
5123 rc = pci_af_flr(dev, 1);
5126 rc = pci_pm_reset(dev, 1);
5129 rc = pci_dev_reset_slot_function(dev, 1);
5133 return pci_parent_bus_reset(dev, 1);
5138 * @dev: PCI device to reset
5152 int pci_reset_function(struct pci_dev *dev)
5156 if (!dev->reset_fn)
5159 pci_dev_lock(dev);
5160 pci_dev_save_and_disable(dev);
5162 rc = __pci_reset_function_locked(dev);
5164 pci_dev_restore(dev);
5165 pci_dev_unlock(dev);
5173 * @dev: PCI device to reset
5188 int pci_reset_function_locked(struct pci_dev *dev)
5192 if (!dev->reset_fn)
5195 pci_dev_save_and_disable(dev);
5197 rc = __pci_reset_function_locked(dev);
5199 pci_dev_restore(dev);
5207 * @dev: PCI device to reset
5211 int pci_try_reset_function(struct pci_dev *dev)
5215 if (!dev->reset_fn)
5218 if (!pci_dev_trylock(dev))
5221 pci_dev_save_and_disable(dev);
5222 rc = __pci_reset_function_locked(dev);
5223 pci_dev_restore(dev);
5224 pci_dev_unlock(dev);
5233 struct pci_dev *dev;
5239 list_for_each_entry(dev, &bus->devices, bus_list) {
5240 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5241 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5251 struct pci_dev *dev;
5254 list_for_each_entry(dev, &bus->devices, bus_list) {
5255 if (dev->subordinate)
5256 pci_bus_lock(dev->subordinate);
5258 pci_dev_lock(dev);
5265 struct pci_dev *dev;
5267 list_for_each_entry(dev, &bus->devices, bus_list) {
5268 if (dev->subordinate)
5269 pci_bus_unlock(dev->subordinate);
5271 pci_dev_unlock(dev);
5279 struct pci_dev *dev;
5284 list_for_each_entry(dev, &bus->devices, bus_list) {
5285 if (dev->subordinate) {
5286 if (!pci_bus_trylock(dev->subordinate))
5288 } else if (!pci_dev_trylock(dev))
5294 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
5295 if (dev->subordinate)
5296 pci_bus_unlock(dev->subordinate);
5298 pci_dev_unlock(dev);
5307 struct pci_dev *dev;
5313 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5314 if (!dev->slot || dev->slot != slot)
5316 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
5317 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
5327 struct pci_dev *dev;
5329 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5330 if (!dev->slot || dev->slot != slot)
5332 if (dev->subordinate)
5333 pci_bus_lock(dev->subordinate);
5335 pci_dev_lock(dev);
5342 struct pci_dev *dev;
5344 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5345 if (!dev->slot || dev->slot != slot)
5347 if (dev->subordinate)
5348 pci_bus_unlock(dev->subordinate);
5349 pci_dev_unlock(dev);
5356 struct pci_dev *dev;
5358 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5359 if (!dev->slot || dev->slot != slot)
5361 if (dev->subordinate) {
5362 if (!pci_bus_trylock(dev->subordinate)) {
5363 pci_dev_unlock(dev);
5366 } else if (!pci_dev_trylock(dev))
5372 list_for_each_entry_continue_reverse(dev,
5374 if (!dev->slot || dev->slot != slot)
5376 if (dev->subordinate)
5377 pci_bus_unlock(dev->subordinate);
5379 pci_dev_unlock(dev);
5386 * the @dev mutex lock for the entire tree.
5390 struct pci_dev *dev;
5392 list_for_each_entry(dev, &bus->devices, bus_list) {
5393 pci_dev_save_and_disable(dev);
5394 if (dev->subordinate)
5395 pci_bus_save_and_disable_locked(dev->subordinate);
5400 * Restore devices from top of the tree down while holding @dev mutex lock
5406 struct pci_dev *dev;
5408 list_for_each_entry(dev, &bus->devices, bus_list) {
5409 pci_dev_restore(dev);
5410 if (dev->subordinate)
5411 pci_bus_restore_locked(dev->subordinate);
5417 * the @dev mutex lock for the entire tree.
5421 struct pci_dev *dev;
5423 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5424 if (!dev->slot || dev->slot != slot)
5426 pci_dev_save_and_disable(dev);
5427 if (dev->subordinate)
5428 pci_bus_save_and_disable_locked(dev->subordinate);
5433 * Restore devices from top of the tree down while holding @dev mutex lock
5439 struct pci_dev *dev;
5441 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
5442 if (!dev->slot || dev->slot != slot)
5444 pci_dev_restore(dev);
5445 if (dev->subordinate)
5446 pci_bus_restore_locked(dev->subordinate);
5626 * @dev: PCI device to query
5631 int pcix_get_max_mmrbc(struct pci_dev *dev)
5636 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5640 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5649 * @dev: PCI device to query
5654 int pcix_get_mmrbc(struct pci_dev *dev)
5659 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5663 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5672 * @dev: PCI device to query
5679 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
5690 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
5694 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
5700 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
5705 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
5710 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
5719 * @dev: PCI device to query
5723 int pcie_get_readrq(struct pci_dev *dev)
5727 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5735 * @dev: PCI device to query
5741 int pcie_set_readrq(struct pci_dev *dev, int rq)
5745 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus);
5756 int mps = pcie_get_mps(dev);
5765 int max_mrrs = pcie_get_readrq(dev);
5768 pci_info(dev, "can't set Max_Read_Request_Size to %d; max is %d\n", rq, max_mrrs);
5773 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5782 * @dev: PCI device to query
5786 int pcie_get_mps(struct pci_dev *dev)
5790 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
5798 * @dev: PCI device to query
5804 int pcie_set_mps(struct pci_dev *dev, int mps)
5813 if (v > dev->pcie_mpss)
5817 ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
5827 * @dev: PCI device to query
5838 u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev,
5854 while (dev) {
5855 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
5868 *limiting_dev = dev;
5875 dev = pci_upstream_bridge(dev);
5884 * @dev: PCI device to query
5889 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev)
5902 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2);
5908 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5920 * @dev: PCI device to query
5925 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev)
5929 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap);
5939 * @dev: PCI device
5947 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
5950 *speed = pcie_get_speed_cap(dev);
5951 *width = pcie_get_width_cap(dev);
5961 * @dev: PCI device to query
5969 void __pcie_print_link_status(struct pci_dev *dev, bool verbose)
5976 bw_cap = pcie_bandwidth_capable(dev, &speed_cap, &width_cap);
5977 bw_avail = pcie_bandwidth_available(dev, &limiting_dev, &speed, &width);
5980 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth (%s x%d link)\n",
5984 pci_info(dev, "%u.%03u Gb/s available PCIe bandwidth, limited by %s x%d link at %s (capable of %u.%03u Gb/s with %s x%d link)\n",
5994 * @dev: PCI device to query
5998 void pcie_print_link_status(struct pci_dev *dev)
6000 __pcie_print_link_status(dev, true);
6006 * @dev: the PCI device for which BAR mask is made
6011 int pci_select_bars(struct pci_dev *dev, unsigned long flags)
6015 if (pci_resource_flags(dev, i) & flags)
6029 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
6033 return arch_set_vga_state(dev, decode, command_bits,
6040 * @dev: the PCI device
6046 int pci_set_vga_state(struct pci_dev *dev, bool decode,
6057 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
6062 pci_read_config_word(dev, PCI_COMMAND, &cmd);
6067 pci_write_config_word(dev, PCI_COMMAND, cmd);
6073 bus = dev->bus;
6099 adev = ACPI_COMPANION(&pdev->dev);
6111 * @dev: the PCI device for which alias is added
6129 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn_from, unsigned nr_devfns)
6136 if (!dev->dma_alias_mask)
6137 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL);
6138 if (!dev->dma_alias_mask) {
6139 pci_warn(dev, "Unable to allocate DMA alias mask\n");
6143 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns);
6146 pci_info(dev, "Enabling fixed DMA alias to %02x.%d\n",
6149 pci_info(dev, "Enabling fixed DMA alias for devfn range from %02x.%d to %02x.%d\n",
6176 void pci_ignore_hotplug(struct pci_dev *dev)
6178 struct pci_dev *bridge = dev->bus->self;
6180 dev->ignore_hotplug = 1;
6189 * @dev: the PCI device that may have a PCI DMA alias
6197 struct pci_dev __weak *pci_real_dma_dev(struct pci_dev *dev)
6199 return dev;
6211 void __weak pci_resource_to_user(const struct pci_dev *dev, int bar,
6224 * @dev: the PCI device to get
6230 static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev,
6262 ret = pci_dev_str_match(dev, p, &p);
6284 static void pci_request_resource_alignment(struct pci_dev *dev, int bar,
6287 struct resource *r = &dev->resource[bar];
6294 pci_info(dev, "BAR%d %pR: ignoring requested alignment %#llx\n",
6331 pci_info(dev, "BAR%d %pR: requesting alignment to %#llx\n",
6353 void pci_reassigndev_resource_alignment(struct pci_dev *dev)
6367 if (dev->is_virtfn)
6371 align = pci_specified_resource_alignment(dev, &resize);
6375 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
6376 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
6377 pci_warn(dev, "Can't reassign resources to host bridge\n");
6381 pci_read_config_word(dev, PCI_COMMAND, &command);
6383 pci_write_config_word(dev, PCI_COMMAND, command);
6386 pci_request_resource_alignment(dev, i, align, resize);
6393 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
6395 r = &dev->resource[i];
6402 pci_disable_bridge_window(dev);