Lines Matching refs:bridge
8 * PCI bridge when the HW doesn't provide such a root port PCI
9 * bridge.
11 * It emulates a PCI bridge by providing a fake PCI configuration
21 #include "pci-bridge-emul.h"
72 * bridge that is not capable of a burst transfer of more than
78 * BIST register: implemented as read-only, as "A bridge that
153 * are RO, and bridge control (31:16) are a mix of RW, RO,
277 * bridge configuration space. The caller needs to have initialized
282 int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
285 BUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END);
287 bridge->conf.class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16);
288 bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
289 bridge->conf.cache_line_size = 0x10;
290 bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);
291 bridge->pci_regs_behavior = kmemdup(pci_regs_behavior,
294 if (!bridge->pci_regs_behavior)
297 if (bridge->has_pcie) {
298 bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START;
299 bridge->conf.status |= cpu_to_le16(PCI_STATUS_CAP_LIST);
300 bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP;
301 bridge->pcie_conf.cap |= cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4);
302 bridge->pcie_cap_regs_behavior =
306 if (!bridge->pcie_cap_regs_behavior) {
307 kfree(bridge->pci_regs_behavior);
311 bridge->pci_regs_behavior[PCI_CACHE_LINE_SIZE / 4].ro &=
313 bridge->pci_regs_behavior[PCI_COMMAND / 4].ro &=
319 bridge->pci_regs_behavior[PCI_PRIMARY_BUS / 4].ro &=
321 bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro &=
324 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].rw &=
327 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].ro &=
329 bridge->pci_regs_behavior[PCI_INTERRUPT_LINE / 4].w1c &=
334 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0;
335 bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0;
346 void pci_bridge_emul_cleanup(struct pci_bridge_emul *bridge)
348 if (bridge->has_pcie)
349 kfree(bridge->pcie_cap_regs_behavior);
350 kfree(bridge->pci_regs_behavior);
356 * configuration space of the fake bridge. It will call back the
359 int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
364 pci_bridge_emul_read_status_t (*read_op)(struct pci_bridge_emul *bridge,
369 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) {
374 if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) {
379 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
381 read_op = bridge->ops->read_pcie;
382 cfgspace = (__le32 *) &bridge->pcie_conf;
383 behavior = bridge->pcie_cap_regs_behavior;
385 read_op = bridge->ops->read_base;
386 cfgspace = (__le32 *) &bridge->conf;
387 behavior = bridge->pci_regs_behavior;
391 ret = read_op(bridge, reg, value);
418 * configuration space of the fake bridge. It will call back the
421 int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
426 void (*write_op)(struct pci_bridge_emul *bridge, int reg,
431 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END)
434 if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END)
448 ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old);
452 if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
454 write_op = bridge->ops->write_pcie;
455 cfgspace = (__le32 *) &bridge->pcie_conf;
456 behavior = bridge->pcie_cap_regs_behavior;
458 write_op = bridge->ops->write_base;
459 cfgspace = (__le32 *) &bridge->conf;
460 behavior = bridge->pci_regs_behavior;
488 write_op(bridge, reg, old, new, mask);